sin.map.eqn

基于Quartus II 5.0编写的正弦波发生器

--P1_q_a[6] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[6]_PORT_A_data_in = VCC;
P1_q_a[6]_PORT_A_data_in_reg = DFFE(P1_q_a[6]_PORT_A_data_in, P1_q_a[6]_clock_0, , , );
P1_q_a[6]_PORT_B_data_in = Q1_ram_rom_data_reg[6];
P1_q_a[6]_PORT_B_data_in_reg = DFFE(P1_q_a[6]_PORT_B_data_in, P1_q_a[6]_clock_1, , , );
P1_q_a[6]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_a[6]_PORT_A_address_reg = DFFE(P1_q_a[6]_PORT_A_address, P1_q_a[6]_clock_0, , , );
P1_q_a[6]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_a[6]_PORT_B_address_reg = DFFE(P1_q_a[6]_PORT_B_address, P1_q_a[6]_clock_1, , , );
P1_q_a[6]_PORT_A_write_enable = GND;
P1_q_a[6]_PORT_A_write_enable_reg = DFFE(P1_q_a[6]_PORT_A_write_enable, P1_q_a[6]_clock_0, , , );
P1_q_a[6]_PORT_B_write_enable = Q1L2;
P1_q_a[6]_PORT_B_write_enable_reg = DFFE(P1_q_a[6]_PORT_B_write_enable, P1_q_a[6]_clock_1, , , );
P1_q_a[6]_clock_0 = clk;
P1_q_a[6]_clock_1 = A1L5;
P1_q_a[6]_PORT_A_data_out = MEMORY(P1_q_a[6]_PORT_A_data_in_reg, P1_q_a[6]_PORT_B_data_in_reg, P1_q_a[6]_PORT_A_address_reg, P1_q_a[6]_PORT_B_address_reg, P1_q_a[6]_PORT_A_write_enable_reg, P1_q_a[6]_PORT_B_write_enable_reg, , , P1_q_a[6]_clock_0, P1_q_a[6]_clock_1, , , , );
P1_q_a[6]_PORT_A_data_out_reg = DFFE(P1_q_a[6]_PORT_A_data_out, P1_q_a[6]_clock_0, , , );
P1_q_a[6] = P1_q_a[6]_PORT_A_data_out_reg[0];

--P1_q_b[6] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_b[6]
P1_q_b[6]_PORT_A_data_in = VCC;
P1_q_b[6]_PORT_A_data_in_reg = DFFE(P1_q_b[6]_PORT_A_data_in, P1_q_b[6]_clock_0, , , );
P1_q_b[6]_PORT_B_data_in = Q1_ram_rom_data_reg[6];
P1_q_b[6]_PORT_B_data_in_reg = DFFE(P1_q_b[6]_PORT_B_data_in, P1_q_b[6]_clock_1, , , );
P1_q_b[6]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_b[6]_PORT_A_address_reg = DFFE(P1_q_b[6]_PORT_A_address, P1_q_b[6]_clock_0, , , );
P1_q_b[6]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_b[6]_PORT_B_address_reg = DFFE(P1_q_b[6]_PORT_B_address, P1_q_b[6]_clock_1, , , );
P1_q_b[6]_PORT_A_write_enable = GND;
P1_q_b[6]_PORT_A_write_enable_reg = DFFE(P1_q_b[6]_PORT_A_write_enable, P1_q_b[6]_clock_0, , , );
P1_q_b[6]_PORT_B_write_enable = Q1L2;
P1_q_b[6]_PORT_B_write_enable_reg = DFFE(P1_q_b[6]_PORT_B_write_enable, P1_q_b[6]_clock_1, , , );
P1_q_b[6]_clock_0 = clk;
P1_q_b[6]_clock_1 = A1L5;
P1_q_b[6]_PORT_B_data_out = MEMORY(P1_q_b[6]_PORT_A_data_in_reg, P1_q_b[6]_PORT_B_data_in_reg, P1_q_b[6]_PORT_A_address_reg, P1_q_b[6]_PORT_B_address_reg, P1_q_b[6]_PORT_A_write_enable_reg, P1_q_b[6]_PORT_B_write_enable_reg, , , P1_q_b[6]_clock_0, P1_q_b[6]_clock_1, , , , );
P1_q_b[6] = P1_q_b[6]_PORT_B_data_out[0];


--P1_q_a[7] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[7]_PORT_A_data_in = VCC;
P1_q_a[7]_PORT_A_data_in_reg = DFFE(P1_q_a[7]_PORT_A_data_in, P1_q_a[7]_clock_0, , , );
P1_q_a[7]_PORT_B_data_in = Q1_ram_rom_data_reg[7];
P1_q_a[7]_PORT_B_data_in_reg = DFFE(P1_q_a[7]_PORT_B_data_in, P1_q_a[7]_clock_1, , , );
P1_q_a[7]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_a[7]_PORT_A_address_reg = DFFE(P1_q_a[7]_PORT_A_address, P1_q_a[7]_clock_0, , , );
P1_q_a[7]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_a[7]_PORT_B_address_reg = DFFE(P1_q_a[7]_PORT_B_address, P1_q_a[7]_clock_1, , , );
P1_q_a[7]_PORT_A_write_enable = GND;
P1_q_a[7]_PORT_A_write_enable_reg = DFFE(P1_q_a[7]_PORT_A_write_enable, P1_q_a[7]_clock_0, , , );
P1_q_a[7]_PORT_B_write_enable = Q1L2;
P1_q_a[7]_PORT_B_write_enable_reg = DFFE(P1_q_a[7]_PORT_B_write_enable, P1_q_a[7]_clock_1, , , );
P1_q_a[7]_clock_0 = clk;
P1_q_a[7]_clock_1 = A1L5;
P1_q_a[7]_PORT_A_data_out = MEMORY(P1_q_a[7]_PORT_A_data_in_reg, P1_q_a[7]_PORT_B_data_in_reg, P1_q_a[7]_PORT_A_address_reg, P1_q_a[7]_PORT_B_address_reg, P1_q_a[7]_PORT_A_write_enable_reg, P1_q_a[7]_PORT_B_write_enable_reg, , , P1_q_a[7]_clock_0, P1_q_a[7]_clock_1, , , , );
P1_q_a[7]_PORT_A_data_out_reg = DFFE(P1_q_a[7]_PORT_A_data_out, P1_q_a[7]_clock_0, , , );
P1_q_a[7] = P1_q_a[7]_PORT_A_data_out_reg[0];

--P1_q_b[7] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_b[7]
P1_q_b[7]_PORT_A_data_in = VCC;
P1_q_b[7]_PORT_A_data_in_reg = DFFE(P1_q_b[7]_PORT_A_data_in, P1_q_b[7]_clock_0, , , );
P1_q_b[7]_PORT_B_data_in = Q1_ram_rom_data_reg[7];
P1_q_b[7]_PORT_B_data_in_reg = DFFE(P1_q_b[7]_PORT_B_data_in, P1_q_b[7]_clock_1, , , );
P1_q_b[7]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_b[7]_PORT_A_address_reg = DFFE(P1_q_b[7]_PORT_A_address, P1_q_b[7]_clock_0, , , );
P1_q_b[7]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_b[7]_PORT_B_address_reg = DFFE(P1_q_b[7]_PORT_B_address, P1_q_b[7]_clock_1, , , );
P1_q_b[7]_PORT_A_write_enable = GND;
P1_q_b[7]_PORT_A_write_enable_reg = DFFE(P1_q_b[7]_PORT_A_write_enable, P1_q_b[7]_clock_0, , , );
P1_q_b[7]_PORT_B_write_enable = Q1L2;
P1_q_b[7]_PORT_B_write_enable_reg = DFFE(P1_q_b[7]_PORT_B_write_enable, P1_q_b[7]_clock_1, , , );
P1_q_b[7]_clock_0 = clk;
P1_q_b[7]_clock_1 = A1L5;
P1_q_b[7]_PORT_B_data_out = MEMORY(P1_q_b[7]_PORT_A_data_in_reg, P1_q_b[7]_PORT_B_data_in_reg, P1_q_b[7]_PORT_A_address_reg, P1_q_b[7]_PORT_B_address_reg, P1_q_b[7]_PORT_A_write_enable_reg, P1_q_b[7]_PORT_B_write_enable_reg, , , P1_q_b[7]_clock_0, P1_q_b[7]_clock_1, , , , );
P1_q_b[7] = P1_q_b[7]_PORT_B_data_out[0];


--A1L6 is altera_internal_jtag~TDO
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1_hub_tdo);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1_hub_tdo);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1_hub_tdo);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1_hub_tdo);


--K1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
--operation mode is normal

K1_state[5] = AMPP_FUNCTION(A1L5, A1L7, K1_state[4], K1_state[3], VCC);


--F1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]
--operation mode is normal

F1_Q[2] = AMPP_FUNCTION(A1L5, F2_Q[2], F6_Q[2], F3_Q[0], !B1L2, B1L71);


--B1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode
--operation mode is normal

B1_jtag_debug_mode = AMPP_FUNCTION(A1L5, B1L22, B1_jtag_debug_mode, B1L32, K1_state[15], K1_state[0]);


--F4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
--operation mode is normal

F4_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, !B1L2, B1L51);


--B1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
--operation mode is normal

B1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, J1_dffs[0], J1_dffs[1], B1L72, B1L82, K1_state[0], K1_state[12]);


--F3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
--operation mode is normal

F3_Q[0] = AMPP_FUNCTION(A1L5, L1_dffe1a[1], !B1L2, B1L1);


--Q1L01 is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~26
--operation mode is normal

Q1L01 = AMPP_FUNCTION(B1_jtag_debug_mode, F4_Q[0], B1_jtag_debug_mode_usr1, F3_Q[0]);


--Q1L2 is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11
--operation mode is normal

Q1L2 = AMPP_FUNCTION(K1_state[5], F1_Q[2], Q1L01);


--D1_dout[6] is reg16b:u2|dout[6]
--operation mode is arithmetic

D1_dout[6]_lut_out = D1_dout[6] $ fword[0];
D1_dout[6] = DFFEAS(D1_dout[6]_lut_out, clk, VCC, , , , , , );

--D1L3 is reg16b:u2|dout[6]~77
--operation mode is arithmetic

D1L3 = CARRY(D1_dout[6] & fword[0]);


--D1_dout[7] is reg16b:u2|dout[7]
--operation mode is arithmetic

D1_dout[7]_carry_eqn = D1L3;
D1_dout[7]_lut_out = D1_dout[7] $ fword[1] $ D1_dout[7]_carry_eqn;
D1_dout[7] = DFFEAS(D1_dout[7]_lut_out, clk, VCC, , , , , , );

--D1L5 is reg16b:u2|dout[7]~81
--operation mode is arithmetic

D1L5 = CARRY(D1_dout[7] & !fword[1] & !D1L3 # !D1_dout[7] & (!D1L3 # !fword[1]));


--D1_dout[8] is reg16b:u2|dout[8]
--operation mode is arithmetic

D1_dout[8]_carry_eqn = D1L5;
D1_dout[8]_lut_out = D1_dout[8] $ fword[2] $ !D1_dout[8]_carry_eqn;
D1_dout[8] = DFFEAS(D1_dout[8]_lut_out, clk, VCC, , , , , , );

--D1L7 is reg16b:u2|dout[8]~85
--operation mode is arithmetic

D1L7 = CARRY(D1_dout[8] & (fword[2] # !D1L5) # !D1_dout[8] & fword[2] & !D1L5);


--D1_dout[9] is reg16b:u2|dout[9]
--operation mode is arithmetic

D1_dout[9]_carry_eqn = D1L7;
D1_dout[9]_lut_out = D1_dout[9] $ fword[3] $ D1_dout[9]_carry_eqn;
D1_dout[9] = DFFEAS(D1_dout[9]_lut_out, clk, VCC, , , , , , );

--D1L9 is reg16b:u2|dout[9]~89
--operation mode is arithmetic

D1L9 = CARRY(D1_dout[9] & !fword[3] & !D1L7 # !D1_dout[9] & (!D1L7 # !fword[3]));


--D1_dout[10] is reg16b:u2|dout[10]
--operation mode is arithmetic

D1_dout[10]_carry_eqn = D1L9;
D1_dout[10]_lut_out = D1_dout[10] $ fword[4] $ !D1_dout[10]_carry_eqn;
D1_dout[10] = DFFEAS(D1_dout[10]_lut_out, clk, VCC, , , , , , );

--D1L11 is reg16b:u2|dout[10]~93
--operation mode is arithmetic

D1L11 = CARRY(D1_dout[10] & (fword[4] # !D1L9) # !D1_dout[10] & fword[4] & !D1L9);


--D1_dout[11] is reg16b:u2|dout[11]
--operation mode is arithmetic

D1_dout[11]_carry_eqn = D1L11;
D1_dout[11]_lut_out = D1_dout[11] $ fword[5] $ D1_dout[11]_carry_eqn;
D1_dout[11] = DFFEAS(D1_dout[11]_lut_out, clk, VCC, , , , , , );

--D1L31 is reg16b:u2|dout[11]~97
--operation mode is arithmetic

D1L31 = CARRY(D1_dout[11] & !fword[5] & !D1L11 # !D1_dout[11] & (!D1L11 # !fword[5]));


--D1_dout[12] is reg16b:u2|dout[12]
--operation mode is arithmetic

D1_dout[12]_carry_eqn = D1L31;
D1_dout[12]_lut_out = D1_dout[12] $ fword[6] $ !D1_dout[12]_carry_eqn;
D1_dout[12] = DFFEAS(D1_dout[12]_lut_out, clk, VCC, , , , , , );

--D1L51 is reg16b:u2|dout[12]~101
--operation mode is arithmetic

D1L51 = CARRY(D1_dout[12] & (fword[6] # !D1L31) # !D1_dout[12] & fword[6] & !D1L31);


--D1_dout[13] is reg16b:u2|dout[13]
--operation mode is arithmetic

D1_dout[13]_carry_eqn = D1L51;
D1_dout[13]_lut_out = D1_dout[13] $ fword[7] $ D1_dout[13]_carry_eqn;
D1_dout[13] = DFFEAS(D1_dout[13]_lut_out, clk, VCC, , , , , , );

--D1L71 is reg16b:u2|dout[13]~105
--operation mode is arithmetic

D1L71 = CARRY(D1_dout[13] & !fword[7] & !D1L51 # !D1_dout[13] & (!D1L51 # !fword[7]));


--D1_dout[14] is reg16b:u2|dout[14]
--operation mode is arithmetic

D1_dout[14]_carry_eqn = D1L71;
D1_dout[14]_lut_out = D1_dout[14] $ (!D1_dout[14]_carry_eqn);
D1_dout[14] = DFFEAS(D1_dout[14]_lut_out, clk, VCC, , , , , , );

--D1L91 is reg16b:u2|dout[14]~109
--operation mode is arithmetic

D1L91 = CARRY(D1_dout[14] & (!D1L71));


--D1_dout[15] is reg16b:u2|dout[15]
--operation mode is normal

D1_dout[15]_carry_eqn = D1L91;