adder16b.vhd

基于Quartus II 5.0编写的正弦波发生器

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity adder16b is
	port( a:in std_logic_vector(15 downto 0);
		b: in std_logic_vector(15 downto 0);
		s: out std_logic_vector(15 downto 0) );
end adder16b;

architecture behav of adder16b is
begin
	s<=a+b;
end behav;