sin.hif

基于Quartus II 5.0编写的正弦波发生器

Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1595
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
data_rom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
data_rom.vhd
1212124636
4
# storage
db|sin.(3).cnf
db|sin.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
data_rom:u3
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|..|..|program files|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|sin.(4).cnf
db|sin.(4).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
D:/altera/shiyan/sin/data/sin_rom.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_cfu
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# include_file {
..|..|..|program files|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|..|..|program files|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
..|..|..|program files|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
..|..|..|program files|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
..|..|..|program files|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
..|..|..|program files|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
..|..|..|program files|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
..|..|..|program files|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
..|..|..|program files|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
..|..|..|program files|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
data_rom:u3|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_cfu
# case_insensitive
# source_file
db|altsyncram_cfu.tdf
1212126212
6
# storage
db|sin.(5).cnf
db|sin.(5).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# hierarchies {
data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated
}
# end
# entity
sld_mod_ram_rom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|program files|altera|quartus50|libraries|megafunctions|sld_mod_ram_rom.vhd
1114012240
4
# storage
db|sin.(7).cnf
db|sin.(7).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_node_info
135818752
PARAMETER_DEC
DEF
sld_ip_version
1
PARAMETER_DEC
DEF
sld_ip_minor_version
0
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
width_word
8
PARAMETER_UNKNOWN
USR
numwords
1024
PARAMETER_UNKNOWN
USR
widthad
10
PARAMETER_UNKNOWN
USR
shift_count_bits
4
PARAMETER_UNKNOWN
USR
cvalue
00000000
PARAMETER_UNKNOWN
USR
is_data_in_ram
1
PARAMETER_UNKNOWN
USR
is_readable
1
PARAMETER_UNKNOWN
USR
node_name
1380928817
PARAMETER_UNKNOWN
USR
}
# include_file {
..|..|..|program files|altera|quartus50|libraries|megafunctions|sld_mod_ram_rom.vhd
1114012240
}
# hierarchies {
data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|program files|altera|quartus50|libraries|megafunctions|sld_rom_sr.vhd
1114012236
4
# storage
db|sin.(8).cnf
db|sin.(8).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
80
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# hierarchies {
data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
}
# end
# entity
sld_hub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|program files|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
4
# storage
db|sin.(9).cnf
db|sin.(9).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
2
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone
PARAMETER_UNKNOWN
USR
n_nodes
1
PARAMETER_UNKNOWN
USR
n_sel_bits
1
PARAMETER_UNKNOWN
USR
n_node_ir_bits
5
PARAMETER_UNKNOWN
USR
node_info
00001000000110000110111000000000
PARAMETER_BIN
USR
}
# include_file {
..|..|..|program files|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
}
# end
# entity
sld_jtag_state_machine
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|program files|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
4
# storage
db|sin.(10).cnf
db|sin.(10).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
1
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
}
# include_file {
..|..|..|program files|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
..|..|..|program files|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage
db|sin.(11).cnf
db|sin.(11).cnf
# user_parameter {
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
enable
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
shiftin
}
# include_file {
..|..|..|program files|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
..|..|..|program files|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
..|..|..|program files|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
}
# end
# entity
lpm_decode
# case_insensitive
# source_file
..|..|..|program files|altera|quartus50|libraries|megafunctions|lpm_decode.tdf
1114012450
6
# storage
db|sin.(12).cnf
db|sin.(12).cnf
# user_parameter {
LPM_WIDTH
3
PARAMETER_DEC
USR
LPM_DECODES
8
PARAMETER_DEC
USR
LPM_PIPELINE
1
PARAMETER_DEC
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_9ie
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq7
}
# include_file {
..|..|..|program files|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
..|..|..|program files|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
..|..|..|program files|altera|quartus50|libraries|megafunctions|declut.inc
1107574136
..|..|..|program files|altera|quartus50|libraries|megafunctions|altshift.inc
1107573438
..|..|..|program files|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
}
# end
# entity
decode_9ie
# case_insensitive
# source_file
db|decode_9ie.tdf
1212126212
6
# storage
db|sin.(13).cnf
db|sin.(13).cnf
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|program files|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1114012236
4
# storage
db|sin.(14).cnf
db|sin.(14).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
1
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|program files|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1114012236
4
# storage
db|sin.(15).cnf
db|sin.(15).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
6
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|program files|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1114012236
4
# storage
db|sin.(16).cnf
db|sin.(16).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
5
PARAMETER_DEC
USR
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|program files|altera|quartus50|libraries|megafunctions|sld_rom_sr.vhd
1114012236
4
# storage
db|sin.(17).cnf
db|sin.(17).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
64
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# end
# entity
altsyncram_aac2
# case_insensitive
# source_file
db|altsyncram_aac2.tdf
1212126212
6
# storage
db|sin.(6).cnf
db|sin.(6).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
clock0
clock1
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
wren_b
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
data|sin_rom.mif
1212140708
}
# hierarchies {
data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1
}
# end
# entity
sin
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sin.vhd
1212467700
4
# storage
db|sin.(0).cnf
db|sin.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
adder16b
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
adder16b.vhd
1212467280
4
# storage
db|sin.(1).cnf
db|sin.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
adder16b:u1
}
# end
# entity
reg16b
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
reg16b.vhd
1212467316
4
# storage
db|sin.(2).cnf
db|sin.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
reg16b:u2
}
# end
# complete