sin.hier_info

基于Quartus II 5.0编写的正弦波发生器

|sin
clk => data_rom:u3.clock
clk => reg16b:u2.load
fword[0] => adder16b:u1.a[6]
fword[1] => adder16b:u1.a[7]
fword[2] => adder16b:u1.a[8]
fword[3] => adder16b:u1.a[9]
fword[4] => adder16b:u1.a[10]
fword[5] => adder16b:u1.a[11]
fword[6] => adder16b:u1.a[12]
fword[7] => adder16b:u1.a[13]
dout[0] <= data_rom:u3.q[0]
dout[1] <= data_rom:u3.q[1]
dout[2] <= data_rom:u3.q[2]
dout[3] <= data_rom:u3.q[3]
dout[4] <= data_rom:u3.q[4]
dout[5] <= data_rom:u3.q[5]
dout[6] <= data_rom:u3.q[6]
dout[7] <= data_rom:u3.q[7]


|sin|adder16b:u1
a[0] => add~0.IN16
a[1] => add~0.IN15
a[2] => add~0.IN14
a[3] => add~0.IN13
a[4] => add~0.IN12
a[5] => add~0.IN11
a[6] => add~0.IN10
a[7] => add~0.IN9
a[8] => add~0.IN8
a[9] => add~0.IN7
a[10] => add~0.IN6
a[11] => add~0.IN5
a[12] => add~0.IN4
a[13] => add~0.IN3
a[14] => add~0.IN2
a[15] => add~0.IN1
b[0] => add~0.IN32
b[1] => add~0.IN31
b[2] => add~0.IN30
b[3] => add~0.IN29
b[4] => add~0.IN28
b[5] => add~0.IN27
b[6] => add~0.IN26
b[7] => add~0.IN25
b[8] => add~0.IN24
b[9] => add~0.IN23
b[10] => add~0.IN22
b[11] => add~0.IN21
b[12] => add~0.IN20
b[13] => add~0.IN19
b[14] => add~0.IN18
b[15] => add~0.IN17
s[0] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[1] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[2] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[3] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[4] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[5] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[6] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[7] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[8] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[9] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[10] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[11] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[12] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[13] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[14] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
s[15] <= add~0.DB_MAX_OUTPUT_PORT_TYPE


|sin|reg16b:u2
load => dout[14]~reg0.CLK
load => dout[13]~reg0.CLK
load => dout[12]~reg0.CLK
load => dout[11]~reg0.CLK
load => dout[10]~reg0.CLK
load => dout[9]~reg0.CLK
load => dout[8]~reg0.CLK
load => dout[7]~reg0.CLK
load => dout[6]~reg0.CLK
load => dout[5]~reg0.CLK
load => dout[4]~reg0.CLK
load => dout[3]~reg0.CLK
load => dout[2]~reg0.CLK
load => dout[1]~reg0.CLK
load => dout[0]~reg0.CLK
load => dout[15]~reg0.CLK
din[0] => dout[0]~reg0.DATAIN
din[1] => dout[1]~reg0.DATAIN
din[2] => dout[2]~reg0.DATAIN
din[3] => dout[3]~reg0.DATAIN
din[4] => dout[4]~reg0.DATAIN
din[5] => dout[5]~reg0.DATAIN
din[6] => dout[6]~reg0.DATAIN
din[7] => dout[7]~reg0.DATAIN
din[8] => dout[8]~reg0.DATAIN
din[9] => dout[9]~reg0.DATAIN
din[10] => dout[10]~reg0.DATAIN
din[11] => dout[11]~reg0.DATAIN
din[12] => dout[12]~reg0.DATAIN
din[13] => dout[13]~reg0.DATAIN
din[14] => dout[14]~reg0.DATAIN
din[15] => dout[15]~reg0.DATAIN
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[10] <= dout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[11] <= dout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[12] <= dout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[13] <= dout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[14] <= dout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[15] <= dout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|sin|data_rom:u3
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|sin|data_rom:u3|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_cfu:auto_generated.address_a[0]
address_a[1] => altsyncram_cfu:auto_generated.address_a[1]
address_a[2] => altsyncram_cfu:auto_generated.address_a[2]
address_a[3] => altsyncram_cfu:auto_generated.address_a[3]
address_a[4] => altsyncram_cfu:auto_generated.address_a[4]
address_a[5] => altsyncram_cfu:auto_generated.address_a[5]
address_a[6] => altsyncram_cfu:auto_generated.address_a[6]
address_a[7] => altsyncram_cfu:auto_generated.address_a[7]
address_a[8] => altsyncram_cfu:auto_generated.address_a[8]
address_a[9] => altsyncram_cfu:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_cfu:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_cfu:auto_generated.q_a[0]
q_a[1] <= altsyncram_cfu:auto_generated.q_a[1]
q_a[2] <= altsyncram_cfu:auto_generated.q_a[2]
q_a[3] <= altsyncram_cfu:auto_generated.q_a[3]
q_a[4] <= altsyncram_cfu:auto_generated.q_a[4]
q_a[5] <= altsyncram_cfu:auto_generated.q_a[5]
q_a[6] <= altsyncram_cfu:auto_generated.q_a[6]
q_a[7] <= altsyncram_cfu:auto_generated.q_a[7]
q_b[0] <= <GND>


|sin|data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated
address_a[0] => altsyncram_aac2:altsyncram1.address_a[0]
address_a[1] => altsyncram_aac2:altsyncram1.address_a[1]
address_a[2] => altsyncram_aac2:altsyncram1.address_a[2]
address_a[3] => altsyncram_aac2:altsyncram1.address_a[3]
address_a[4] => altsyncram_aac2:altsyncram1.address_a[4]
address_a[5] => altsyncram_aac2:altsyncram1.address_a[5]
address_a[6] => altsyncram_aac2:altsyncram1.address_a[6]
address_a[7] => altsyncram_aac2:altsyncram1.address_a[7]
address_a[8] => altsyncram_aac2:altsyncram1.address_a[8]
address_a[9] => altsyncram_aac2:altsyncram1.address_a[9]
clock0 => altsyncram_aac2:altsyncram1.clock0
q_a[0] <= altsyncram_aac2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_aac2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_aac2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_aac2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_aac2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_aac2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_aac2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_aac2:altsyncram1.q_a[7]


|sin|data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_a[8] => ram_block3a0.PORTAADDR8
address_a[8] => ram_block3a1.PORTAADDR8
address_a[8] => ram_block3a2.PORTAADDR8
address_a[8] => ram_block3a3.PORTAADDR8
address_a[8] => ram_block3a4.PORTAADDR8
address_a[8] => ram_block3a5.PORTAADDR8
address_a[8] => ram_block3a6.PORTAADDR8
address_a[8] => ram_block3a7.PORTAADDR8
address_a[9] => ram_block3a0.PORTAADDR9
address_a[9] => ram_block3a1.PORTAADDR9
address_a[9] => ram_block3a2.PORTAADDR9
address_a[9] => ram_block3a3.PORTAADDR9
address_a[9] => ram_block3a4.PORTAADDR9
address_a[9] => ram_block3a5.PORTAADDR9
address_a[9] => ram_block3a6.PORTAADDR9
address_a[9] => ram_block3a7.PORTAADDR9
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3