sin.fit.qmsg

基于Quartus II 5.0编写的正弦波发生器

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.022 ns register register " "Info: Estimated most critical path is register to register delay of 4.022 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] 1 REG LAB_X17_Y7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y7; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(0.442 ns) 1.506 ns sld_hub:sld_hub_inst\|hub_tdo~359 2 COMB LAB_X17_Y6 1 " "Info: 2: + IC(1.064 ns) + CELL(0.442 ns) = 1.506 ns; Loc. = LAB_X17_Y6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~359'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.506 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.442 ns) 2.936 ns sld_hub:sld_hub_inst\|hub_tdo~360 3 COMB LAB_X18_Y7 1 " "Info: 3: + IC(0.988 ns) + CELL(0.442 ns) = 2.936 ns; Loc. = LAB_X18_Y7; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~360'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.430 ns" { sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.777 ns) + CELL(0.309 ns) 4.022 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LAB_X19_Y7 0 " "Info: 4: + IC(0.777 ns) + CELL(0.309 ns) = 4.022 ns; Loc. = LAB_X19_Y7; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.086 ns" { sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.193 ns 29.66 % " "Info: Total cell delay = 1.193 ns ( 29.66 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.829 ns 70.34 % " "Info: Total interconnect delay = 2.829 ns ( 70.34 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "4.022 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 2 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 2%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\] -- routed using non-global resources" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\]" } } } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/altera/shiyan/sin/sin.fld" "" { Floorplan "D:/altera/shiyan/sin/sin.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\] -- routed using non-global resources" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/altera/shiyan/sin/sin.fld" "" { Floorplan "D:/altera/shiyan/sin/sin.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\] -- routed using non-global resources" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\]" } } } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/altera/shiyan/sin/sin.fld" "" { Floorplan "D:/altera/shiyan/sin/sin.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\] -- routed using non-global resources" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\]" } } } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/altera/shiyan/sin/sin.fld" "" { Floorplan "D:/altera/shiyan/sin/sin.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\] -- routed using non-global resources" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\]" } } } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/altera/shiyan/sin/sin.fld" "" { Floorplan "D:/altera/shiyan/sin/sin.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] } "NODE_NAME" } }  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/altera/shiyan/sin/sin.fld" "" { Floorplan "D:/altera/shiyan/sin/sin.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode -- routed using non-global resources" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode" } } } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 382 -1 0 } } { "D:/altera/shiyan/sin/sin.fld" "" { Floorplan "D:/altera/shiyan/sin/sin.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } }  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]" } } } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } } { "D:/altera/shiyan/sin/sin.fld" "" { Floorplan "D:/altera/shiyan/sin/sin.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 03 12:35:12 2008 " "Info: Processing ended: Tue Jun 03 12:35:12 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}