sin.fit.qmsg

基于Quartus II 5.0编写的正弦波发生器

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0}  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1 " "Info: Destination \"data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~11 " "Info: Destination \"data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~11\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~12 " "Info: Destination \"data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~12\" may be non-global or may not use global clock" {  } {  } 0}  } { { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "16 unused 3.30 8 8 0 " "Info: Number of I/O pins in group: 16 (unused VREF, 3.30 VCCIO, 8 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 19 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  19 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 4 26 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  26 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}