sin.map.qmsg

基于Quartus II 5.0编写的正弦波发生器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 03 12:35:00 2008 " "Info: Processing started: Tue Jun 03 12:35:00 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sin -c sin " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sin -c sin" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sin-one " "Info: Found design unit 1: sin-one" {  } { { "sin.vhd" "" { Text "D:/altera/shiyan/sin/sin.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sin " "Info: Found entity 1: sin" {  } { { "sin.vhd" "" { Text "D:/altera/shiyan/sin/sin.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg16b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg16b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg16b-behav " "Info: Found design unit 1: reg16b-behav" {  } { { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 reg16b " "Info: Found entity 1: reg16b" {  } { { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder16b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adder16b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder16b-behav " "Info: Found design unit 1: adder16b-behav" {  } { { "adder16b.vhd" "" { Text "D:/altera/shiyan/sin/adder16b.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 adder16b " "Info: Found entity 1: adder16b" {  } { { "adder16b.vhd" "" { Text "D:/altera/shiyan/sin/adder16b.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_rom.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file data_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 data_rom-SYN " "Info: Found design unit 1: data_rom-SYN" {  } { { "data_rom.vhd" "" { Text "D:/altera/shiyan/sin/data_rom.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 data_rom " "Info: Found entity 1: data_rom" {  } { { "data_rom.vhd" "" { Text "D:/altera/shiyan/sin/data_rom.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sin " "Info: Elaborating entity \"sin\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder16b adder16b:u1 " "Info: Elaborating entity \"adder16b\" for hierarchy \"adder16b:u1\"" {  } { { "sin.vhd" "u1" { Text "D:/altera/shiyan/sin/sin.vhd" 34 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg16b reg16b:u2 " "Info: Elaborating entity \"reg16b\" for hierarchy \"reg16b:u2\"" {  } { { "sin.vhd" "u2" { Text "D:/altera/shiyan/sin/sin.vhd" 35 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_rom data_rom:u3 " "Info: Elaborating entity \"data_rom\" for hierarchy \"data_rom:u3\"" {  } { { "sin.vhd" "u3" { Text "D:/altera/shiyan/sin/sin.vhd" 36 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram data_rom:u3\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"data_rom:u3\|altsyncram:altsyncram_component\"" {  } { { "data_rom.vhd" "altsyncram_component" { Text "D:/altera/shiyan/sin/data_rom.vhd" 80 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_cfu.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_cfu.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_cfu " "Info: Found entity 1: altsyncram_cfu" {  } { { "db/altsyncram_cfu.tdf" "" { Text "D:/altera/shiyan/sin/db/altsyncram_cfu.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_cfu data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated " "Info: Elaborating entity \"altsyncram_cfu\" for hierarchy \"data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_aac2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_aac2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_aac2 " "Info: Found entity 1: altsyncram_aac2" {  } { { "db/altsyncram_aac2.tdf" "" { Text "D:/altera/shiyan/sin/db/altsyncram_aac2.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_aac2 data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1 " "Info: Elaborating entity \"altsyncram_aac2\" for hierarchy \"data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\"" {  } { { "db/altsyncram_cfu.tdf" "altsyncram1" { Text "D:/altera/shiyan/sin/db/altsyncram_cfu.tdf" 34 2 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mod_ram_rom_pack " "Info: Found design unit 1: sld_mod_ram_rom_pack" {  } { { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 4 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_mod_ram_rom-rtl " "Info: Found design unit 2: sld_mod_ram_rom-rtl" {  } { { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 72 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mod_ram_rom " "Info: Found entity 1: sld_mod_ram_rom" {  } { { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_cfu.tdf" "mgl_prim2" { Text "D:/altera/shiyan/sin/db/altsyncram_cfu.tdf" 35 2 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../program files/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "sld_rom_sr.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "sld_rom_sr.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr " "Info: Elaborating entity \"sld_rom_sr\" for hierarchy \"data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\"" {  } { { "sld_mod_ram_rom.vhd" "\\ram_rom_logic_gen:name_gen:info_rom_sr" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 650 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1012 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 997 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../program files/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 37 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../program files/altera/quartus50/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" 62 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_9ie.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_9ie " "Info: Found entity 1: decode_9ie" {  } { { "db/decode_9ie.tdf" "" { Text "D:/altera/shiyan/sin/db/decode_9ie.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg16b:u2\|dout\[5\] data_in GND " "Warning: Reduced register \"reg16b:u2\|dout\[5\]\" with stuck data_in port to stuck value GND" {  } { { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg16b:u2\|dout\[4\] data_in GND " "Warning: Reduced register \"reg16b:u2\|dout\[4\]\" with stuck data_in port to stuck value GND" {  } { { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg16b:u2\|dout\[3\] data_in GND " "Warning: Reduced register \"reg16b:u2\|dout\[3\]\" with stuck data_in port to stuck value GND" {  } { { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg16b:u2\|dout\[2\] data_in GND " "Warning: Reduced register \"reg16b:u2\|dout\[2\]\" with stuck data_in port to stuck value GND" {  } { { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg16b:u2\|dout\[1\] data_in GND " "Warning: Reduced register \"reg16b:u2\|dout\[1\]\" with stuck data_in port to stuck value GND" {  } { { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg16b:u2\|dout\[0\] data_in GND " "Warning: Reduced register \"reg16b:u2\|dout\[0\]\" with stuck data_in port to stuck value GND" {  } { { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "211 " "Info: Implemented 211 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "181 " "Info: Implemented 181 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 03 12:35:05 2008 " "Info: Processing ended: Tue Jun 03 12:35:05 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}