sin.tan.qmsg

基于Quartus II 5.0编写的正弦波发生器

{ "Info" "ITDB_TH_RESULT" "data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[9\] altera_internal_jtag altera_internal_jtag~TCKUTAP 3.329 ns register " "Info: th for register \"data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[9\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 3.329 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.272 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 144 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 144; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[9\] 2 REG LC_X16_Y6_N9 4 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X16_Y6_N9; Fanout = 4; REG Node = 'data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[9\]'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] } "NODE_NAME" } "" } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.49 % " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns 86.51 % " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.958 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y6_N1 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 10; PIN Node = 'altera_internal_jtag'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { altera_internal_jtag } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.843 ns) + CELL(0.115 ns) 1.958 ns data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[9\] 2 REG LC_X16_Y6_N9 4 " "Info: 2: + IC(1.843 ns) + CELL(0.115 ns) = 1.958 ns; Loc. = LC_X16_Y6_N9; Fanout = 4; REG Node = 'data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[9\]'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.958 ns" { altera_internal_jtag data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] } "NODE_NAME" } "" } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 5.87 % " "Info: Total cell delay = 0.115 ns ( 5.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.843 ns 94.13 % " "Info: Total interconnect delay = 1.843 ns ( 94.13 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.958 ns" { altera_internal_jtag data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "1.958 ns" { altera_internal_jtag data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] } { 0.000ns 1.843ns } { 0.000ns 0.115ns } } }  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.958 ns" { altera_internal_jtag data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "1.958 ns" { altera_internal_jtag data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] } { 0.000ns 1.843ns } { 0.000ns 0.115ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 03 12:35:16 2008 " "Info: Processing ended: Tue Jun 03 12:35:16 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}