sin.tan.qmsg

基于Quartus II 5.0编写的正弦波发生器

{ "Info" "ITDB_TSU_RESULT" "reg16b:u2\|dout\[11\] fword\[1\] clk 6.180 ns register " "Info: tsu for register \"reg16b:u2\|dout\[11\]\" (data pin = \"fword\[1\]\", clock pin = \"clk\") is 6.180 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.925 ns + Longest pin register " "Info: + Longest pin to register delay is 8.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns fword\[1\] 1 PIN PIN_122 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_122; Fanout = 3; PIN Node = 'fword\[1\]'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { fword[1] } "NODE_NAME" } "" } } { "sin.vhd" "" { Text "D:/altera/shiyan/sin/sin.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.854 ns) + CELL(0.423 ns) 7.752 ns reg16b:u2\|dout\[7\]~81 2 COMB LC_X15_Y7_N1 2 " "Info: 2: + IC(5.854 ns) + CELL(0.423 ns) = 7.752 ns; Loc. = LC_X15_Y7_N1; Fanout = 2; COMB Node = 'reg16b:u2\|dout\[7\]~81'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "6.277 ns" { fword[1] reg16b:u2|dout[7]~81 } "NODE_NAME" } "" } } { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 7.830 ns reg16b:u2\|dout\[8\]~85 3 COMB LC_X15_Y7_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 7.830 ns; Loc. = LC_X15_Y7_N2; Fanout = 2; COMB Node = 'reg16b:u2\|dout\[8\]~85'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "0.078 ns" { reg16b:u2|dout[7]~81 reg16b:u2|dout[8]~85 } "NODE_NAME" } "" } } { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 7.908 ns reg16b:u2\|dout\[9\]~89 4 COMB LC_X15_Y7_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 7.908 ns; Loc. = LC_X15_Y7_N3; Fanout = 2; COMB Node = 'reg16b:u2\|dout\[9\]~89'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "0.078 ns" { reg16b:u2|dout[8]~85 reg16b:u2|dout[9]~89 } "NODE_NAME" } "" } } { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 8.086 ns reg16b:u2\|dout\[10\]~93 5 COMB LC_X15_Y7_N4 5 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 8.086 ns; Loc. = LC_X15_Y7_N4; Fanout = 5; COMB Node = 'reg16b:u2\|dout\[10\]~93'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "0.178 ns" { reg16b:u2|dout[9]~89 reg16b:u2|dout[10]~93 } "NODE_NAME" } "" } } { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 8.925 ns reg16b:u2\|dout\[11\] 6 REG LC_X15_Y7_N5 5 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 8.925 ns; Loc. = LC_X15_Y7_N5; Fanout = 5; REG Node = 'reg16b:u2\|dout\[11\]'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "0.839 ns" { reg16b:u2|dout[10]~93 reg16b:u2|dout[11] } "NODE_NAME" } "" } } { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.071 ns 34.41 % " "Info: Total cell delay = 3.071 ns ( 34.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.854 ns 65.59 % " "Info: Total interconnect delay = 5.854 ns ( 65.59 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "8.925 ns" { fword[1] reg16b:u2|dout[7]~81 reg16b:u2|dout[8]~85 reg16b:u2|dout[9]~89 reg16b:u2|dout[10]~93 reg16b:u2|dout[11] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "8.925 ns" { fword[1] fword[1]~out0 reg16b:u2|dout[7]~81 reg16b:u2|dout[8]~85 reg16b:u2|dout[9]~89 reg16b:u2|dout[10]~93 reg16b:u2|dout[11] } { 0.000ns 0.000ns 5.854ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.423ns 0.078ns 0.078ns 0.178ns 0.839ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 56 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 56; CLK Node = 'clk'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { clk } "NODE_NAME" } "" } } { "sin.vhd" "" { Text "D:/altera/shiyan/sin/sin.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns reg16b:u2\|dout\[11\] 2 REG LC_X15_Y7_N5 5 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y7_N5; Fanout = 5; REG Node = 'reg16b:u2\|dout\[11\]'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.313 ns" { clk reg16b:u2|dout[11] } "NODE_NAME" } "" } } { "reg16b.vhd" "" { Text "D:/altera/shiyan/sin/reg16b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 78.36 % " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns 21.64 % " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "2.782 ns" { clk reg16b:u2|dout[11] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 reg16b:u2|dout[11] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "8.925 ns" { fword[1] reg16b:u2|dout[7]~81 reg16b:u2|dout[8]~85 reg16b:u2|dout[9]~89 reg16b:u2|dout[10]~93 reg16b:u2|dout[11] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "8.925 ns" { fword[1] fword[1]~out0 reg16b:u2|dout[7]~81 reg16b:u2|dout[8]~85 reg16b:u2|dout[9]~89 reg16b:u2|dout[10]~93 reg16b:u2|dout[11] } { 0.000ns 0.000ns 5.854ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.423ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "2.782 ns" { clk reg16b:u2|dout[11] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 reg16b:u2|dout[11] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[3\] data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|q_a\[3\] 7.966 ns memory " "Info: tco from clock \"clk\" to destination pin \"dout\[3\]\" through memory \"data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|q_a\[3\]\" is 7.966 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.778 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 56 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 56; CLK Node = 'clk'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { clk } "NODE_NAME" } "" } } { "sin.vhd" "" { Text "D:/altera/shiyan/sin/sin.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.708 ns) 2.778 ns data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|q_a\[3\] 2 MEM M4K_X13_Y6 1 " "Info: 2: + IC(0.601 ns) + CELL(0.708 ns) = 2.778 ns; Loc. = M4K_X13_Y6; Fanout = 1; MEM Node = 'data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|q_a\[3\]'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.309 ns" { clk data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[3] } "NODE_NAME" } "" } } { "db/altsyncram_aac2.tdf" "" { Text "D:/altera/shiyan/sin/db/altsyncram_aac2.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns 78.37 % " "Info: Total cell delay = 2.177 ns ( 78.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.63 % " "Info: Total interconnect delay = 0.601 ns ( 21.63 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "2.778 ns" { clk data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.778 ns" { clk clk~out0 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[3] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.708ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_aac2.tdf" "" { Text "D:/altera/shiyan/sin/db/altsyncram_aac2.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.538 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.538 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|q_a\[3\] 1 MEM M4K_X13_Y6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X13_Y6; Fanout = 1; MEM Node = 'data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|q_a\[3\]'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[3] } "NODE_NAME" } "" } } { "db/altsyncram_aac2.tdf" "" { Text "D:/altera/shiyan/sin/db/altsyncram_aac2.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.326 ns) + CELL(2.108 ns) 4.538 ns dout\[3\] 2 PIN PIN_52 0 " "Info: 2: + IC(2.326 ns) + CELL(2.108 ns) = 4.538 ns; Loc. = PIN_52; Fanout = 0; PIN Node = 'dout\[3\]'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "4.434 ns" { data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[3] dout[3] } "NODE_NAME" } "" } } { "sin.vhd" "" { Text "D:/altera/shiyan/sin/sin.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.212 ns 48.74 % " "Info: Total cell delay = 2.212 ns ( 48.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.326 ns 51.26 % " "Info: Total interconnect delay = 2.326 ns ( 51.26 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "4.538 ns" { data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[3] dout[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.538 ns" { data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[3] dout[3] } { 0.000ns 2.326ns } { 0.104ns 2.108ns } } }  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "2.778 ns" { clk data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.778 ns" { clk clk~out0 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[3] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.708ns } } } { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "4.538 ns" { data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[3] dout[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.538 ns" { data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[3] dout[3] } { 0.000ns 2.326ns } { 0.104ns 2.108ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y6_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_90 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_90; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 100.00 % " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.124ns } } }  } 0}