sin.tan.qmsg

基于Quartus II 5.0编写的正弦波发生器

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "sin.vhd" "" { Text "D:/altera/shiyan/sin/sin.vhd" 7 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|ram_block3a4~porta_datain_reg3 memory data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|ram_block3a4~porta_memory_reg3 197.01 MHz 5.076 ns Internal " "Info: Clock \"clk\" has Internal fmax of 197.01 MHz between source memory \"data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|ram_block3a4~porta_datain_reg3\" and destination memory \"data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|ram_block3a4~porta_memory_reg3\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|ram_block3a4~porta_datain_reg3 1 MEM M4K_X13_Y7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y7; Fanout = 1; MEM Node = 'data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|ram_block3a4~porta_datain_reg3'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_aac2.tdf" "" { Text "D:/altera/shiyan/sin/db/altsyncram_aac2.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|ram_block3a4~porta_memory_reg3 2 MEM M4K_X13_Y7 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y7; Fanout = 0; MEM Node = 'data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|ram_block3a4~porta_memory_reg3'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "4.319 ns" { data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_memory_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_aac2.tdf" "" { Text "D:/altera/shiyan/sin/db/altsyncram_aac2.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns 100.00 % " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "4.319 ns" { data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_memory_reg3 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_memory_reg3 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.779 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 56 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 56; CLK Node = 'clk'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { clk } "NODE_NAME" } "" } } { "sin.vhd" "" { Text "D:/altera/shiyan/sin/sin.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.708 ns) 2.779 ns data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|ram_block3a4~porta_memory_reg3 2 MEM M4K_X13_Y7 0 " "Info: 2: + IC(0.602 ns) + CELL(0.708 ns) = 2.779 ns; Loc. = M4K_X13_Y7; Fanout = 0; MEM Node = 'data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|ram_block3a4~porta_memory_reg3'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.310 ns" { clk data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_memory_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_aac2.tdf" "" { Text "D:/altera/shiyan/sin/db/altsyncram_aac2.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns 78.34 % " "Info: Total cell delay = 2.177 ns ( 78.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns 21.66 % " "Info: Total interconnect delay = 0.602 ns ( 21.66 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "2.779 ns" { clk data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_memory_reg3 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.779 ns" { clk clk~out0 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_memory_reg3 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.708ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.793 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 56 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 56; CLK Node = 'clk'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { clk } "NODE_NAME" } "" } } { "sin.vhd" "" { Text "D:/altera/shiyan/sin/sin.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.722 ns) 2.793 ns data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|ram_block3a4~porta_datain_reg3 2 MEM M4K_X13_Y7 1 " "Info: 2: + IC(0.602 ns) + CELL(0.722 ns) = 2.793 ns; Loc. = M4K_X13_Y7; Fanout = 1; MEM Node = 'data_rom:u3\|altsyncram:altsyncram_component\|altsyncram_cfu:auto_generated\|altsyncram_aac2:altsyncram1\|ram_block3a4~porta_datain_reg3'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.324 ns" { clk data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_aac2.tdf" "" { Text "D:/altera/shiyan/sin/db/altsyncram_aac2.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 78.45 % " "Info: Total cell delay = 2.191 ns ( 78.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns 21.55 % " "Info: Total interconnect delay = 0.602 ns ( 21.55 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "2.793 ns" { clk data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~out0 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "2.779 ns" { clk data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_memory_reg3 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.779 ns" { clk clk~out0 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_memory_reg3 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.708ns } } } { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "2.793 ns" { clk data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~out0 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_aac2.tdf" "" { Text "D:/altera/shiyan/sin/db/altsyncram_aac2.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_aac2.tdf" "" { Text "D:/altera/shiyan/sin/db/altsyncram_aac2.tdf" 182 2 0 } }  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "4.319 ns" { data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_memory_reg3 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_memory_reg3 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "2.779 ns" { clk data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_memory_reg3 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.779 ns" { clk clk~out0 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_memory_reg3 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.708ns } } } { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "2.793 ns" { clk data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~out0 data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ram_block3a4~porta_datain_reg3 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] register sld_hub:sld_hub_inst\|hub_tdo 99.27 MHz 10.074 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 99.27 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 10.074 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.776 ns + Longest register register " "Info: + Longest register to register delay is 4.776 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] 1 REG LC_X17_Y7_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y7_N0; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.648 ns) + CELL(0.114 ns) 1.762 ns sld_hub:sld_hub_inst\|hub_tdo~359 2 COMB LC_X17_Y6_N8 1 " "Info: 2: + IC(1.648 ns) + CELL(0.114 ns) = 1.762 ns; Loc. = LC_X17_Y6_N8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~359'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.762 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.221 ns) + CELL(0.590 ns) 3.573 ns sld_hub:sld_hub_inst\|hub_tdo~360 3 COMB LC_X18_Y7_N5 1 " "Info: 3: + IC(1.221 ns) + CELL(0.590 ns) = 3.573 ns; Loc. = LC_X18_Y7_N5; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~360'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.811 ns" { sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.478 ns) 4.776 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X19_Y7_N8 0 " "Info: 4: + IC(0.725 ns) + CELL(0.478 ns) = 4.776 ns; Loc. = LC_X19_Y7_N8; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "1.203 ns" { sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.182 ns 24.75 % " "Info: Total cell delay = 1.182 ns ( 24.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.594 ns 75.25 % " "Info: Total interconnect delay = 3.594 ns ( 75.25 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "4.776 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.776 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.648ns 1.221ns 0.725ns } { 0.000ns 0.114ns 0.590ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.272 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 144 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 144; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X19_Y7_N8 0 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X19_Y7_N8; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.49 % " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns 86.51 % " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.272 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 144 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 144; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] 2 REG LC_X17_Y7_N0 4 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X17_Y7_N0; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]'" {  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.49 % " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns 86.51 % " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "4.776 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.776 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.648ns 1.221ns 0.725ns } { 0.000ns 0.114ns 0.590ns 0.478ns } } } { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "D:/altera/shiyan/sin/db/sin_cmp.qrpt" "" { Report "D:/altera/shiyan/sin/db/sin_cmp.qrpt" Compiler "sin" "UNKNOWN" "V1" "D:/altera/shiyan/sin/db/sin.quartus_db" { Floorplan "D:/altera/shiyan/sin/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0}