sin.fit.eqn

基于Quartus II 5.0编写的正弦波发生器

P1_q_a[4]_clock_1 = GLOBAL(A1L5);
P1_q_a[4]_PORT_A_data_out = MEMORY(P1_q_a[4]_PORT_A_data_in_reg, P1_q_a[4]_PORT_B_data_in_reg, P1_q_a[4]_PORT_A_address_reg, P1_q_a[4]_PORT_B_address_reg, P1_q_a[4]_PORT_A_write_enable_reg, P1_q_a[4]_PORT_B_write_enable_reg, , , P1_q_a[4]_clock_0, P1_q_a[4]_clock_1, , , , );
P1_q_a[4]_PORT_A_data_out_reg = DFFE(P1_q_a[4]_PORT_A_data_out, P1_q_a[4]_clock_0, , , );
P1_q_a[6] = P1_q_a[4]_PORT_A_data_out_reg[2];

--P1_q_a[5] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[5] at M4K_X13_Y7
P1_q_a[4]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_a[4]_PORT_A_data_in_reg = DFFE(P1_q_a[4]_PORT_A_data_in, P1_q_a[4]_clock_0, , , );
P1_q_a[4]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[4], Q1_ram_rom_data_reg[5], Q1_ram_rom_data_reg[6], Q1_ram_rom_data_reg[7]);
P1_q_a[4]_PORT_B_data_in_reg = DFFE(P1_q_a[4]_PORT_B_data_in, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_a[4]_PORT_A_address_reg = DFFE(P1_q_a[4]_PORT_A_address, P1_q_a[4]_clock_0, , , );
P1_q_a[4]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_a[4]_PORT_B_address_reg = DFFE(P1_q_a[4]_PORT_B_address, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_PORT_A_write_enable = GND;
P1_q_a[4]_PORT_A_write_enable_reg = DFFE(P1_q_a[4]_PORT_A_write_enable, P1_q_a[4]_clock_0, , , );
P1_q_a[4]_PORT_B_write_enable = Q1L2;
P1_q_a[4]_PORT_B_write_enable_reg = DFFE(P1_q_a[4]_PORT_B_write_enable, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_clock_0 = GLOBAL(clk);
P1_q_a[4]_clock_1 = GLOBAL(A1L5);
P1_q_a[4]_PORT_A_data_out = MEMORY(P1_q_a[4]_PORT_A_data_in_reg, P1_q_a[4]_PORT_B_data_in_reg, P1_q_a[4]_PORT_A_address_reg, P1_q_a[4]_PORT_B_address_reg, P1_q_a[4]_PORT_A_write_enable_reg, P1_q_a[4]_PORT_B_write_enable_reg, , , P1_q_a[4]_clock_0, P1_q_a[4]_clock_1, , , , );
P1_q_a[4]_PORT_A_data_out_reg = DFFE(P1_q_a[4]_PORT_A_data_out, P1_q_a[4]_clock_0, , , );
P1_q_a[5] = P1_q_a[4]_PORT_A_data_out_reg[1];

--P1_q_b[7] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_b[7] at M4K_X13_Y7
P1_q_b[4]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_b[4]_PORT_A_data_in_reg = DFFE(P1_q_b[4]_PORT_A_data_in, P1_q_b[4]_clock_0, , , );
P1_q_b[4]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[4], Q1_ram_rom_data_reg[5], Q1_ram_rom_data_reg[6], Q1_ram_rom_data_reg[7]);
P1_q_b[4]_PORT_B_data_in_reg = DFFE(P1_q_b[4]_PORT_B_data_in, P1_q_b[4]_clock_1, , , );
P1_q_b[4]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_b[4]_PORT_A_address_reg = DFFE(P1_q_b[4]_PORT_A_address, P1_q_b[4]_clock_0, , , );
P1_q_b[4]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_b[4]_PORT_B_address_reg = DFFE(P1_q_b[4]_PORT_B_address, P1_q_b[4]_clock_1, , , );
P1_q_b[4]_PORT_A_write_enable = GND;
P1_q_b[4]_PORT_A_write_enable_reg = DFFE(P1_q_b[4]_PORT_A_write_enable, P1_q_b[4]_clock_0, , , );
P1_q_b[4]_PORT_B_write_enable = Q1L2;
P1_q_b[4]_PORT_B_write_enable_reg = DFFE(P1_q_b[4]_PORT_B_write_enable, P1_q_b[4]_clock_1, , , );
P1_q_b[4]_clock_0 = GLOBAL(clk);
P1_q_b[4]_clock_1 = GLOBAL(A1L5);
P1_q_b[4]_PORT_B_data_out = MEMORY(P1_q_b[4]_PORT_A_data_in_reg, P1_q_b[4]_PORT_B_data_in_reg, P1_q_b[4]_PORT_A_address_reg, P1_q_b[4]_PORT_B_address_reg, P1_q_b[4]_PORT_A_write_enable_reg, P1_q_b[4]_PORT_B_write_enable_reg, , , P1_q_b[4]_clock_0, P1_q_b[4]_clock_1, , , , );
P1_q_b[7] = P1_q_b[4]_PORT_B_data_out[3];

--P1_q_b[6] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_b[6] at M4K_X13_Y7
P1_q_b[4]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_b[4]_PORT_A_data_in_reg = DFFE(P1_q_b[4]_PORT_A_data_in, P1_q_b[4]_clock_0, , , );
P1_q_b[4]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[4], Q1_ram_rom_data_reg[5], Q1_ram_rom_data_reg[6], Q1_ram_rom_data_reg[7]);
P1_q_b[4]_PORT_B_data_in_reg = DFFE(P1_q_b[4]_PORT_B_data_in, P1_q_b[4]_clock_1, , , );
P1_q_b[4]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_b[4]_PORT_A_address_reg = DFFE(P1_q_b[4]_PORT_A_address, P1_q_b[4]_clock_0, , , );
P1_q_b[4]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_b[4]_PORT_B_address_reg = DFFE(P1_q_b[4]_PORT_B_address, P1_q_b[4]_clock_1, , , );
P1_q_b[4]_PORT_A_write_enable = GND;
P1_q_b[4]_PORT_A_write_enable_reg = DFFE(P1_q_b[4]_PORT_A_write_enable, P1_q_b[4]_clock_0, , , );
P1_q_b[4]_PORT_B_write_enable = Q1L2;
P1_q_b[4]_PORT_B_write_enable_reg = DFFE(P1_q_b[4]_PORT_B_write_enable, P1_q_b[4]_clock_1, , , );
P1_q_b[4]_clock_0 = GLOBAL(clk);
P1_q_b[4]_clock_1 = GLOBAL(A1L5);
P1_q_b[4]_PORT_B_data_out = MEMORY(P1_q_b[4]_PORT_A_data_in_reg, P1_q_b[4]_PORT_B_data_in_reg, P1_q_b[4]_PORT_A_address_reg, P1_q_b[4]_PORT_B_address_reg, P1_q_b[4]_PORT_A_write_enable_reg, P1_q_b[4]_PORT_B_write_enable_reg, , , P1_q_b[4]_clock_0, P1_q_b[4]_clock_1, , , , );
P1_q_b[6] = P1_q_b[4]_PORT_B_data_out[2];

--P1_q_b[5] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_b[5] at M4K_X13_Y7
P1_q_b[4]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_b[4]_PORT_A_data_in_reg = DFFE(P1_q_b[4]_PORT_A_data_in, P1_q_b[4]_clock_0, , , );
P1_q_b[4]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[4], Q1_ram_rom_data_reg[5], Q1_ram_rom_data_reg[6], Q1_ram_rom_data_reg[7]);
P1_q_b[4]_PORT_B_data_in_reg = DFFE(P1_q_b[4]_PORT_B_data_in, P1_q_b[4]_clock_1, , , );
P1_q_b[4]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_b[4]_PORT_A_address_reg = DFFE(P1_q_b[4]_PORT_A_address, P1_q_b[4]_clock_0, , , );
P1_q_b[4]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_b[4]_PORT_B_address_reg = DFFE(P1_q_b[4]_PORT_B_address, P1_q_b[4]_clock_1, , , );
P1_q_b[4]_PORT_A_write_enable = GND;
P1_q_b[4]_PORT_A_write_enable_reg = DFFE(P1_q_b[4]_PORT_A_write_enable, P1_q_b[4]_clock_0, , , );
P1_q_b[4]_PORT_B_write_enable = Q1L2;
P1_q_b[4]_PORT_B_write_enable_reg = DFFE(P1_q_b[4]_PORT_B_write_enable, P1_q_b[4]_clock_1, , , );
P1_q_b[4]_clock_0 = GLOBAL(clk);
P1_q_b[4]_clock_1 = GLOBAL(A1L5);
P1_q_b[4]_PORT_B_data_out = MEMORY(P1_q_b[4]_PORT_A_data_in_reg, P1_q_b[4]_PORT_B_data_in_reg, P1_q_b[4]_PORT_A_address_reg, P1_q_b[4]_PORT_B_address_reg, P1_q_b[4]_PORT_A_write_enable_reg, P1_q_b[4]_PORT_B_write_enable_reg, , , P1_q_b[4]_clock_0, P1_q_b[4]_clock_1, , , , );
P1_q_b[5] = P1_q_b[4]_PORT_B_data_out[1];


--A1L6 is altera_internal_jtag~TDO at JTAG_X1_Y6_N1
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1_hub_tdo);

--A1L7 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y6_N1
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1_hub_tdo);

--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y6_N1
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1_hub_tdo);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y6_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1_hub_tdo);


--K1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] at LC_X20_Y5_N6
--operation mode is normal

K1_state[5] = AMPP_FUNCTION(A1L5, A1L7, K1_state[3], K1_state[4], VCC);


--F1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X17_Y7_N0
--operation mode is normal

F1_Q[2] = AMPP_FUNCTION(A1L5, F2_Q[2], F6_Q[2], F3_Q[0], !B1L2, B1L71);


--B1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode at LC_X18_Y6_N6
--operation mode is normal

B1_jtag_debug_mode = AMPP_FUNCTION(A1L5, B1_jtag_debug_mode, B1L22, B1L32, K1_state[15], K1_state[0]);


--B1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LC_X19_Y6_N4
--operation mode is normal

B1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, J1_dffs[0], B1L82, B1L72, J1_dffs[1], K1_state[0], K1_state[12]);


--Q1L01 is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~26 at LC_X18_Y6_N5
--operation mode is normal

Q1L01 = AMPP_FUNCTION(B1_jtag_debug_mode_usr1, F4_Q[0], B1_jtag_debug_mode);

--F3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] at LC_X18_Y6_N5
--operation mode is normal

F3_Q[0] = AMPP_FUNCTION(A1L5, L1_dffe1a[1], !B1L2, GND, B1L1);


--Q1L2 is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11 at LC_X18_Y6_N4
--operation mode is normal

Q1L2 = AMPP_FUNCTION(Q1L01, F1_Q[2], K1_state[5]);


--D1_dout[6] is reg16b:u2|dout[6] at LC_X15_Y7_N0
--operation mode is arithmetic

D1_dout[6]_lut_out = fword[0] $ D1_dout[6];
D1_dout[6] = DFFEAS(D1_dout[6]_lut_out, GLOBAL(clk), VCC, , , , , , );

--D1L3 is reg16b:u2|dout[6]~77 at LC_X15_Y7_N0
--operation mode is arithmetic

D1L3_cout_0 = fword[0] & D1_dout[6];
D1L3 = CARRY(D1L3_cout_0);

--D1L4 is reg16b:u2|dout[6]~77COUT1_117 at LC_X15_Y7_N0
--operation mode is arithmetic

D1L4_cout_1 = fword[0] & D1_dout[6];
D1L4 = CARRY(D1L4_cout_1);


--D1_dout[7] is reg16b:u2|dout[7] at LC_X15_Y7_N1
--operation mode is arithmetic

D1_dout[7]_lut_out = D1_dout[7] $ fword[1] $ D1L3;
D1_dout[7] = DFFEAS(D1_dout[7]_lut_out, GLOBAL(clk), VCC, , , , , , );

--D1L6 is reg16b:u2|dout[7]~81 at LC_X15_Y7_N1
--operation mode is arithmetic

D1L6_cout_0 = D1_dout[7] & !fword[1] & !D1L3 # !D1_dout[7] & (!D1L3 # !fword[1]);
D1L6 = CARRY(D1L6_cout_0);

--D1L7 is reg16b:u2|dout[7]~81COUT1_118 at LC_X15_Y7_N1
--operation mode is arithmetic

D1L7_cout_1 = D1_dout[7] & !fword[1] & !D1L4 # !D1_dout[7] & (!D1L4 # !fword[1]);
D1L7 = CARRY(D1L7_cout_1);


--D1_dout[8] is reg16b:u2|dout[8] at LC_X15_Y7_N2
--operation mode is arithmetic

D1_dout[8]_lut_out = D1_dout[8] $ fword[2] $ !D1L6;
D1_dout[8] = DFFEAS(D1_dout[8]_lut_out, GLOBAL(clk), VCC, , , , , , );

--D1L9 is reg16b:u2|dout[8]~85 at LC_X15_Y7_N2
--operation mode is arithmetic

D1L9_cout_0 = D1_dout[8] & (fword[2] # !D1L6) # !D1_dout[8] & fword[2] & !D1L6;
D1L9 = CARRY(D1L9_cout_0);

--D1L01 is reg16b:u2|dout[8]~85COUT1_119 at LC_X15_Y7_N2
--operation mode is arithmetic

D1L01_cout_1 = D1_dout[8] & (fword[2] # !D1L7) # !D1_dout[8] & fword[2] & !D1L7;
D1L01 = CARRY(D1L01_cout_1);


--D1_dout[9] is reg16b:u2|dout[9] at LC_X15_Y7_N3
--operation mode is arithmetic

D1_dout[9]_lut_out = fword[3] $ D1_dout[9] $ D1L9;
D1_dout[9] = DFFEAS(D1_dout[9]_lut_out, GLOBAL(clk), VCC, , , , , , );

--D1L21 is reg16b:u2|dout[9]~89 at LC_X15_Y7_N3
--operation mode is arithmetic

D1L21_cout_0 = fword[3] & !D1_dout[9] & !D1L9 # !fword[3] & (!D1L9 # !D1_dout[9]);
D1L21 = CARRY(D1L21_cout_0);

--D1L31 is reg16b:u2|dout[9]~89COUT1_120 at LC_X15_Y7_N3
--operation mode is arithmetic

D1L31_cout_1 = fword[3] & !D1_dout[9] & !D1L01 # !fword[3] & (!D1L01 # !D1_dout[9]);
D1L31 = CARRY(D1L31_cout_1);


--D1_dout[10] is reg16b:u2|dout[10] at LC_X15_Y7_N4
--operation mode is arithmetic

D1_dout[10]_lut_out = fword[4] $ D1_dout[10] $ !D1L21;
D1_dout[10] = DFFEAS(D1_dout[10]_lut_out, GLOBAL(clk), VCC, , , , , , );

--D1L51 is reg16b:u2|dout[10]~93 at LC_X15_Y7_N4
--operation mode is arithmetic

D1L51 = CARRY(fword[4] & (D1_dout[10] # !D1L31) # !fword[4] & D1_dout[10] & !D1L31);


--D1_dout[11] is reg16b:u2|dout[11] at LC_X15_Y7_N5
--operation mode is arithmetic

D1_dout[11]_carry_eqn = D1L51;
D1_dout[11]_lut_out = fword[5] $ D1_dout[11] $ D1_dout[11]_carry_eqn;
D1_dout[11] = DFFEAS(D1_dout[11]_lut_out, GLOBAL(clk), VCC, , , , , , );

--D1L71 is reg16b:u2|dout[11]~97 at LC_X15_Y7_N5
--operation mode is arithmetic

D1L71_cout_0 = fword[5] & !D1_dout[11] & !D1L51 # !fword[5] & (!D1L51 # !D1_dout[11]);
D1L71 = CARRY(D1L71_cout_0);

--D1L81 is reg16b:u2|dout[11]~97COUT1_121 at LC_X15_Y7_N5
--operation mode is arithmetic

D1L81_cout_1 = fword[5] & !D1_dout[11] & !D1L51 # !fword[5] & (!D1L51 # !D1_dout[11]);
D1L81 = CARRY(D1L81_cout_1);