sin.fit.eqn

基于Quartus II 5.0编写的正弦波发生器

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--P1_q_a[0] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[0] at M4K_X13_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_a[0]_PORT_A_data_in_reg = DFFE(P1_q_a[0]_PORT_A_data_in, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[0], Q1_ram_rom_data_reg[1], Q1_ram_rom_data_reg[2], Q1_ram_rom_data_reg[3]);
P1_q_a[0]_PORT_B_data_in_reg = DFFE(P1_q_a[0]_PORT_B_data_in, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_a[0]_PORT_A_address_reg = DFFE(P1_q_a[0]_PORT_A_address, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_a[0]_PORT_B_address_reg = DFFE(P1_q_a[0]_PORT_B_address, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_write_enable = GND;
P1_q_a[0]_PORT_A_write_enable_reg = DFFE(P1_q_a[0]_PORT_A_write_enable, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_write_enable = Q1L2;
P1_q_a[0]_PORT_B_write_enable_reg = DFFE(P1_q_a[0]_PORT_B_write_enable, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_clock_0 = GLOBAL(clk);
P1_q_a[0]_clock_1 = GLOBAL(A1L5);
P1_q_a[0]_PORT_A_data_out = MEMORY(P1_q_a[0]_PORT_A_data_in_reg, P1_q_a[0]_PORT_B_data_in_reg, P1_q_a[0]_PORT_A_address_reg, P1_q_a[0]_PORT_B_address_reg, P1_q_a[0]_PORT_A_write_enable_reg, P1_q_a[0]_PORT_B_write_enable_reg, , , P1_q_a[0]_clock_0, P1_q_a[0]_clock_1, , , , );
P1_q_a[0]_PORT_A_data_out_reg = DFFE(P1_q_a[0]_PORT_A_data_out, P1_q_a[0]_clock_0, , , );
P1_q_a[0] = P1_q_a[0]_PORT_A_data_out_reg[0];

--P1_q_b[0] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_b[0] at M4K_X13_Y6
P1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_b[0]_PORT_A_data_in_reg = DFFE(P1_q_b[0]_PORT_A_data_in, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[0], Q1_ram_rom_data_reg[1], Q1_ram_rom_data_reg[2], Q1_ram_rom_data_reg[3]);
P1_q_b[0]_PORT_B_data_in_reg = DFFE(P1_q_b[0]_PORT_B_data_in, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_b[0]_PORT_A_address_reg = DFFE(P1_q_b[0]_PORT_A_address, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_b[0]_PORT_B_address_reg = DFFE(P1_q_b[0]_PORT_B_address, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_PORT_A_write_enable = GND;
P1_q_b[0]_PORT_A_write_enable_reg = DFFE(P1_q_b[0]_PORT_A_write_enable, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_write_enable = Q1L2;
P1_q_b[0]_PORT_B_write_enable_reg = DFFE(P1_q_b[0]_PORT_B_write_enable, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_clock_0 = GLOBAL(clk);
P1_q_b[0]_clock_1 = GLOBAL(A1L5);
P1_q_b[0]_PORT_B_data_out = MEMORY(P1_q_b[0]_PORT_A_data_in_reg, P1_q_b[0]_PORT_B_data_in_reg, P1_q_b[0]_PORT_A_address_reg, P1_q_b[0]_PORT_B_address_reg, P1_q_b[0]_PORT_A_write_enable_reg, P1_q_b[0]_PORT_B_write_enable_reg, , , P1_q_b[0]_clock_0, P1_q_b[0]_clock_1, , , , );
P1_q_b[0] = P1_q_b[0]_PORT_B_data_out[0];

--P1_q_a[3] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[3] at M4K_X13_Y6
P1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_a[0]_PORT_A_data_in_reg = DFFE(P1_q_a[0]_PORT_A_data_in, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[0], Q1_ram_rom_data_reg[1], Q1_ram_rom_data_reg[2], Q1_ram_rom_data_reg[3]);
P1_q_a[0]_PORT_B_data_in_reg = DFFE(P1_q_a[0]_PORT_B_data_in, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_a[0]_PORT_A_address_reg = DFFE(P1_q_a[0]_PORT_A_address, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_a[0]_PORT_B_address_reg = DFFE(P1_q_a[0]_PORT_B_address, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_write_enable = GND;
P1_q_a[0]_PORT_A_write_enable_reg = DFFE(P1_q_a[0]_PORT_A_write_enable, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_write_enable = Q1L2;
P1_q_a[0]_PORT_B_write_enable_reg = DFFE(P1_q_a[0]_PORT_B_write_enable, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_clock_0 = GLOBAL(clk);
P1_q_a[0]_clock_1 = GLOBAL(A1L5);
P1_q_a[0]_PORT_A_data_out = MEMORY(P1_q_a[0]_PORT_A_data_in_reg, P1_q_a[0]_PORT_B_data_in_reg, P1_q_a[0]_PORT_A_address_reg, P1_q_a[0]_PORT_B_address_reg, P1_q_a[0]_PORT_A_write_enable_reg, P1_q_a[0]_PORT_B_write_enable_reg, , , P1_q_a[0]_clock_0, P1_q_a[0]_clock_1, , , , );
P1_q_a[0]_PORT_A_data_out_reg = DFFE(P1_q_a[0]_PORT_A_data_out, P1_q_a[0]_clock_0, , , );
P1_q_a[3] = P1_q_a[0]_PORT_A_data_out_reg[3];

--P1_q_a[2] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[2] at M4K_X13_Y6
P1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_a[0]_PORT_A_data_in_reg = DFFE(P1_q_a[0]_PORT_A_data_in, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[0], Q1_ram_rom_data_reg[1], Q1_ram_rom_data_reg[2], Q1_ram_rom_data_reg[3]);
P1_q_a[0]_PORT_B_data_in_reg = DFFE(P1_q_a[0]_PORT_B_data_in, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_a[0]_PORT_A_address_reg = DFFE(P1_q_a[0]_PORT_A_address, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_a[0]_PORT_B_address_reg = DFFE(P1_q_a[0]_PORT_B_address, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_write_enable = GND;
P1_q_a[0]_PORT_A_write_enable_reg = DFFE(P1_q_a[0]_PORT_A_write_enable, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_write_enable = Q1L2;
P1_q_a[0]_PORT_B_write_enable_reg = DFFE(P1_q_a[0]_PORT_B_write_enable, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_clock_0 = GLOBAL(clk);
P1_q_a[0]_clock_1 = GLOBAL(A1L5);
P1_q_a[0]_PORT_A_data_out = MEMORY(P1_q_a[0]_PORT_A_data_in_reg, P1_q_a[0]_PORT_B_data_in_reg, P1_q_a[0]_PORT_A_address_reg, P1_q_a[0]_PORT_B_address_reg, P1_q_a[0]_PORT_A_write_enable_reg, P1_q_a[0]_PORT_B_write_enable_reg, , , P1_q_a[0]_clock_0, P1_q_a[0]_clock_1, , , , );
P1_q_a[0]_PORT_A_data_out_reg = DFFE(P1_q_a[0]_PORT_A_data_out, P1_q_a[0]_clock_0, , , );
P1_q_a[2] = P1_q_a[0]_PORT_A_data_out_reg[2];

--P1_q_a[1] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[1] at M4K_X13_Y6
P1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_a[0]_PORT_A_data_in_reg = DFFE(P1_q_a[0]_PORT_A_data_in, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[0], Q1_ram_rom_data_reg[1], Q1_ram_rom_data_reg[2], Q1_ram_rom_data_reg[3]);
P1_q_a[0]_PORT_B_data_in_reg = DFFE(P1_q_a[0]_PORT_B_data_in, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_a[0]_PORT_A_address_reg = DFFE(P1_q_a[0]_PORT_A_address, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_a[0]_PORT_B_address_reg = DFFE(P1_q_a[0]_PORT_B_address, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_write_enable = GND;
P1_q_a[0]_PORT_A_write_enable_reg = DFFE(P1_q_a[0]_PORT_A_write_enable, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_write_enable = Q1L2;
P1_q_a[0]_PORT_B_write_enable_reg = DFFE(P1_q_a[0]_PORT_B_write_enable, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_clock_0 = GLOBAL(clk);
P1_q_a[0]_clock_1 = GLOBAL(A1L5);
P1_q_a[0]_PORT_A_data_out = MEMORY(P1_q_a[0]_PORT_A_data_in_reg, P1_q_a[0]_PORT_B_data_in_reg, P1_q_a[0]_PORT_A_address_reg, P1_q_a[0]_PORT_B_address_reg, P1_q_a[0]_PORT_A_write_enable_reg, P1_q_a[0]_PORT_B_write_enable_reg, , , P1_q_a[0]_clock_0, P1_q_a[0]_clock_1, , , , );
P1_q_a[0]_PORT_A_data_out_reg = DFFE(P1_q_a[0]_PORT_A_data_out, P1_q_a[0]_clock_0, , , );
P1_q_a[1] = P1_q_a[0]_PORT_A_data_out_reg[1];

--P1_q_b[3] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_b[3] at M4K_X13_Y6
P1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_b[0]_PORT_A_data_in_reg = DFFE(P1_q_b[0]_PORT_A_data_in, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[0], Q1_ram_rom_data_reg[1], Q1_ram_rom_data_reg[2], Q1_ram_rom_data_reg[3]);
P1_q_b[0]_PORT_B_data_in_reg = DFFE(P1_q_b[0]_PORT_B_data_in, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_b[0]_PORT_A_address_reg = DFFE(P1_q_b[0]_PORT_A_address, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_b[0]_PORT_B_address_reg = DFFE(P1_q_b[0]_PORT_B_address, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_PORT_A_write_enable = GND;
P1_q_b[0]_PORT_A_write_enable_reg = DFFE(P1_q_b[0]_PORT_A_write_enable, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_write_enable = Q1L2;
P1_q_b[0]_PORT_B_write_enable_reg = DFFE(P1_q_b[0]_PORT_B_write_enable, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_clock_0 = GLOBAL(clk);
P1_q_b[0]_clock_1 = GLOBAL(A1L5);
P1_q_b[0]_PORT_B_data_out = MEMORY(P1_q_b[0]_PORT_A_data_in_reg, P1_q_b[0]_PORT_B_data_in_reg, P1_q_b[0]_PORT_A_address_reg, P1_q_b[0]_PORT_B_address_reg, P1_q_b[0]_PORT_A_write_enable_reg, P1_q_b[0]_PORT_B_write_enable_reg, , , P1_q_b[0]_clock_0, P1_q_b[0]_clock_1, , , , );
P1_q_b[3] = P1_q_b[0]_PORT_B_data_out[3];

--P1_q_b[2] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_b[2] at M4K_X13_Y6
P1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_b[0]_PORT_A_data_in_reg = DFFE(P1_q_b[0]_PORT_A_data_in, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[0], Q1_ram_rom_data_reg[1], Q1_ram_rom_data_reg[2], Q1_ram_rom_data_reg[3]);
P1_q_b[0]_PORT_B_data_in_reg = DFFE(P1_q_b[0]_PORT_B_data_in, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_b[0]_PORT_A_address_reg = DFFE(P1_q_b[0]_PORT_A_address, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_b[0]_PORT_B_address_reg = DFFE(P1_q_b[0]_PORT_B_address, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_PORT_A_write_enable = GND;
P1_q_b[0]_PORT_A_write_enable_reg = DFFE(P1_q_b[0]_PORT_A_write_enable, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_write_enable = Q1L2;
P1_q_b[0]_PORT_B_write_enable_reg = DFFE(P1_q_b[0]_PORT_B_write_enable, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_clock_0 = GLOBAL(clk);
P1_q_b[0]_clock_1 = GLOBAL(A1L5);
P1_q_b[0]_PORT_B_data_out = MEMORY(P1_q_b[0]_PORT_A_data_in_reg, P1_q_b[0]_PORT_B_data_in_reg, P1_q_b[0]_PORT_A_address_reg, P1_q_b[0]_PORT_B_address_reg, P1_q_b[0]_PORT_A_write_enable_reg, P1_q_b[0]_PORT_B_write_enable_reg, , , P1_q_b[0]_clock_0, P1_q_b[0]_clock_1, , , , );
P1_q_b[2] = P1_q_b[0]_PORT_B_data_out[2];

--P1_q_b[1] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_b[1] at M4K_X13_Y6
P1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_b[0]_PORT_A_data_in_reg = DFFE(P1_q_b[0]_PORT_A_data_in, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[0], Q1_ram_rom_data_reg[1], Q1_ram_rom_data_reg[2], Q1_ram_rom_data_reg[3]);
P1_q_b[0]_PORT_B_data_in_reg = DFFE(P1_q_b[0]_PORT_B_data_in, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_b[0]_PORT_A_address_reg = DFFE(P1_q_b[0]_PORT_A_address, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_b[0]_PORT_B_address_reg = DFFE(P1_q_b[0]_PORT_B_address, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_PORT_A_write_enable = GND;
P1_q_b[0]_PORT_A_write_enable_reg = DFFE(P1_q_b[0]_PORT_A_write_enable, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_write_enable = Q1L2;
P1_q_b[0]_PORT_B_write_enable_reg = DFFE(P1_q_b[0]_PORT_B_write_enable, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_clock_0 = GLOBAL(clk);
P1_q_b[0]_clock_1 = GLOBAL(A1L5);
P1_q_b[0]_PORT_B_data_out = MEMORY(P1_q_b[0]_PORT_A_data_in_reg, P1_q_b[0]_PORT_B_data_in_reg, P1_q_b[0]_PORT_A_address_reg, P1_q_b[0]_PORT_B_address_reg, P1_q_b[0]_PORT_A_write_enable_reg, P1_q_b[0]_PORT_B_write_enable_reg, , , P1_q_b[0]_clock_0, P1_q_b[0]_clock_1, , , , );
P1_q_b[1] = P1_q_b[0]_PORT_B_data_out[1];


--P1_q_a[4] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[4] at M4K_X13_Y7
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[4]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_a[4]_PORT_A_data_in_reg = DFFE(P1_q_a[4]_PORT_A_data_in, P1_q_a[4]_clock_0, , , );
P1_q_a[4]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[4], Q1_ram_rom_data_reg[5], Q1_ram_rom_data_reg[6], Q1_ram_rom_data_reg[7]);
P1_q_a[4]_PORT_B_data_in_reg = DFFE(P1_q_a[4]_PORT_B_data_in, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_a[4]_PORT_A_address_reg = DFFE(P1_q_a[4]_PORT_A_address, P1_q_a[4]_clock_0, , , );
P1_q_a[4]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_a[4]_PORT_B_address_reg = DFFE(P1_q_a[4]_PORT_B_address, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_PORT_A_write_enable = GND;
P1_q_a[4]_PORT_A_write_enable_reg = DFFE(P1_q_a[4]_PORT_A_write_enable, P1_q_a[4]_clock_0, , , );
P1_q_a[4]_PORT_B_write_enable = Q1L2;
P1_q_a[4]_PORT_B_write_enable_reg = DFFE(P1_q_a[4]_PORT_B_write_enable, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_clock_0 = GLOBAL(clk);
P1_q_a[4]_clock_1 = GLOBAL(A1L5);
P1_q_a[4]_PORT_A_data_out = MEMORY(P1_q_a[4]_PORT_A_data_in_reg, P1_q_a[4]_PORT_B_data_in_reg, P1_q_a[4]_PORT_A_address_reg, P1_q_a[4]_PORT_B_address_reg, P1_q_a[4]_PORT_A_write_enable_reg, P1_q_a[4]_PORT_B_write_enable_reg, , , P1_q_a[4]_clock_0, P1_q_a[4]_clock_1, , , , );
P1_q_a[4]_PORT_A_data_out_reg = DFFE(P1_q_a[4]_PORT_A_data_out, P1_q_a[4]_clock_0, , , );
P1_q_a[4] = P1_q_a[4]_PORT_A_data_out_reg[0];

--P1_q_b[4] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_b[4] at M4K_X13_Y7
P1_q_b[4]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_b[4]_PORT_A_data_in_reg = DFFE(P1_q_b[4]_PORT_A_data_in, P1_q_b[4]_clock_0, , , );
P1_q_b[4]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[4], Q1_ram_rom_data_reg[5], Q1_ram_rom_data_reg[6], Q1_ram_rom_data_reg[7]);
P1_q_b[4]_PORT_B_data_in_reg = DFFE(P1_q_b[4]_PORT_B_data_in, P1_q_b[4]_clock_1, , , );
P1_q_b[4]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_b[4]_PORT_A_address_reg = DFFE(P1_q_b[4]_PORT_A_address, P1_q_b[4]_clock_0, , , );
P1_q_b[4]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_b[4]_PORT_B_address_reg = DFFE(P1_q_b[4]_PORT_B_address, P1_q_b[4]_clock_1, , , );
P1_q_b[4]_PORT_A_write_enable = GND;
P1_q_b[4]_PORT_A_write_enable_reg = DFFE(P1_q_b[4]_PORT_A_write_enable, P1_q_b[4]_clock_0, , , );
P1_q_b[4]_PORT_B_write_enable = Q1L2;
P1_q_b[4]_PORT_B_write_enable_reg = DFFE(P1_q_b[4]_PORT_B_write_enable, P1_q_b[4]_clock_1, , , );
P1_q_b[4]_clock_0 = GLOBAL(clk);
P1_q_b[4]_clock_1 = GLOBAL(A1L5);
P1_q_b[4]_PORT_B_data_out = MEMORY(P1_q_b[4]_PORT_A_data_in_reg, P1_q_b[4]_PORT_B_data_in_reg, P1_q_b[4]_PORT_A_address_reg, P1_q_b[4]_PORT_B_address_reg, P1_q_b[4]_PORT_A_write_enable_reg, P1_q_b[4]_PORT_B_write_enable_reg, , , P1_q_b[4]_clock_0, P1_q_b[4]_clock_1, , , , );
P1_q_b[4] = P1_q_b[4]_PORT_B_data_out[0];

--P1_q_a[7] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[7] at M4K_X13_Y7
P1_q_a[4]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_a[4]_PORT_A_data_in_reg = DFFE(P1_q_a[4]_PORT_A_data_in, P1_q_a[4]_clock_0, , , );
P1_q_a[4]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[4], Q1_ram_rom_data_reg[5], Q1_ram_rom_data_reg[6], Q1_ram_rom_data_reg[7]);
P1_q_a[4]_PORT_B_data_in_reg = DFFE(P1_q_a[4]_PORT_B_data_in, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_a[4]_PORT_A_address_reg = DFFE(P1_q_a[4]_PORT_A_address, P1_q_a[4]_clock_0, , , );
P1_q_a[4]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_a[4]_PORT_B_address_reg = DFFE(P1_q_a[4]_PORT_B_address, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_PORT_A_write_enable = GND;
P1_q_a[4]_PORT_A_write_enable_reg = DFFE(P1_q_a[4]_PORT_A_write_enable, P1_q_a[4]_clock_0, , , );
P1_q_a[4]_PORT_B_write_enable = Q1L2;
P1_q_a[4]_PORT_B_write_enable_reg = DFFE(P1_q_a[4]_PORT_B_write_enable, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_clock_0 = GLOBAL(clk);
P1_q_a[4]_clock_1 = GLOBAL(A1L5);
P1_q_a[4]_PORT_A_data_out = MEMORY(P1_q_a[4]_PORT_A_data_in_reg, P1_q_a[4]_PORT_B_data_in_reg, P1_q_a[4]_PORT_A_address_reg, P1_q_a[4]_PORT_B_address_reg, P1_q_a[4]_PORT_A_write_enable_reg, P1_q_a[4]_PORT_B_write_enable_reg, , , P1_q_a[4]_clock_0, P1_q_a[4]_clock_1, , , , );
P1_q_a[4]_PORT_A_data_out_reg = DFFE(P1_q_a[4]_PORT_A_data_out, P1_q_a[4]_clock_0, , , );
P1_q_a[7] = P1_q_a[4]_PORT_A_data_out_reg[3];

--P1_q_a[6] is data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|q_a[6] at M4K_X13_Y7
P1_q_a[4]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P1_q_a[4]_PORT_A_data_in_reg = DFFE(P1_q_a[4]_PORT_A_data_in, P1_q_a[4]_clock_0, , , );
P1_q_a[4]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[4], Q1_ram_rom_data_reg[5], Q1_ram_rom_data_reg[6], Q1_ram_rom_data_reg[7]);
P1_q_a[4]_PORT_B_data_in_reg = DFFE(P1_q_a[4]_PORT_B_data_in, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_PORT_A_address = BUS(D1_dout[6], D1_dout[7], D1_dout[8], D1_dout[9], D1_dout[10], D1_dout[11], D1_dout[12], D1_dout[13], D1_dout[14], D1_dout[15]);
P1_q_a[4]_PORT_A_address_reg = DFFE(P1_q_a[4]_PORT_A_address, P1_q_a[4]_clock_0, , , );
P1_q_a[4]_PORT_B_address = BUS(Q1_ram_rom_addr_reg[0], Q1_ram_rom_addr_reg[1], Q1_ram_rom_addr_reg[2], Q1_ram_rom_addr_reg[3], Q1_ram_rom_addr_reg[4], Q1_ram_rom_addr_reg[5], Q1_ram_rom_addr_reg[6], Q1_ram_rom_addr_reg[7], Q1_ram_rom_addr_reg[8], Q1_ram_rom_addr_reg[9]);
P1_q_a[4]_PORT_B_address_reg = DFFE(P1_q_a[4]_PORT_B_address, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_PORT_A_write_enable = GND;
P1_q_a[4]_PORT_A_write_enable_reg = DFFE(P1_q_a[4]_PORT_A_write_enable, P1_q_a[4]_clock_0, , , );
P1_q_a[4]_PORT_B_write_enable = Q1L2;
P1_q_a[4]_PORT_B_write_enable_reg = DFFE(P1_q_a[4]_PORT_B_write_enable, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_clock_0 = GLOBAL(clk);