sin.map.rpt

基于Quartus II 5.0编写的正弦波发生器

; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst ;
+--------------------------+----------------------------------+---------+
; Parameter Name           ; Value                            ; Type    ;
+--------------------------+----------------------------------+---------+
; sld_hub_ip_version       ; 1                                ; Untyped ;
; sld_hub_ip_minor_version ; 2                                ; Untyped ;
; sld_common_ip_version    ; 0                                ; Untyped ;
; device_family            ; Cyclone                          ; Untyped ;
; n_nodes                  ; 1                                ; Untyped ;
; n_sel_bits               ; 1                                ; Untyped ;
; n_node_ir_bits           ; 5                                ; Untyped ;
; node_info                ; 00001000000110000110111000000000 ; Binary  ;
+--------------------------+----------------------------------+---------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------+
; In-System Memory Content Editor Settings                                                                                              ;
+----------------+-------------+-------+-------+------------+---------------------------------------------------------------------------+
; Instance Index ; Instance ID ; Width ; Depth ; Mode       ; Hierarchy Location                                                        ;
+----------------+-------------+-------+-------+------------+---------------------------------------------------------------------------+
; 0              ; ROM1        ; 8     ; 1024  ; Read/Write ; data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated ;
+----------------+-------------+-------+-------+------------+---------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/altera/shiyan/sin/sin.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Jun 03 12:35:00 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sin -c sin
Info: Found 2 design units, including 1 entities, in source file sin.vhd
    Info: Found design unit 1: sin-one
    Info: Found entity 1: sin
Info: Found 2 design units, including 1 entities, in source file reg16b.vhd
    Info: Found design unit 1: reg16b-behav
    Info: Found entity 1: reg16b
Info: Found 2 design units, including 1 entities, in source file adder16b.vhd
    Info: Found design unit 1: adder16b-behav
    Info: Found entity 1: adder16b
Info: Found 2 design units, including 1 entities, in source file data_rom.vhd
    Info: Found design unit 1: data_rom-SYN
    Info: Found entity 1: data_rom
Info: Elaborating entity "sin" for the top level hierarchy
Info: Elaborating entity "adder16b" for hierarchy "adder16b:u1"
Info: Elaborating entity "reg16b" for hierarchy "reg16b:u2"
Info: Elaborating entity "data_rom" for hierarchy "data_rom:u3"
Info: Found 1 design units, including 1 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "data_rom:u3|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_cfu.tdf
    Info: Found entity 1: altsyncram_cfu
Info: Elaborating entity "altsyncram_cfu" for hierarchy "data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_aac2.tdf
    Info: Found entity 1: altsyncram_aac2
Info: Elaborating entity "altsyncram_aac2" for hierarchy "data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1"
Info: Found 3 design units, including 1 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd
    Info: Found design unit 1: sld_mod_ram_rom_pack
    Info: Found design unit 2: sld_mod_ram_rom-rtl
    Info: Found entity 1: sld_mod_ram_rom
Info: Elaborating entity "sld_mod_ram_rom" for hierarchy "data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2"
Info: Found 2 design units, including 1 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Elaborating entity "sld_rom_sr" for hierarchy "data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr"
Info: Found 6 design units, including 2 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Found 1 design units, including 1 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 1 design units, including 1 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf
    Info: Found entity 1: decode_9ie
Info: Found 2 design units, including 1 entities, in source file ../../../program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd
    Info: Found design unit 1: sld_dffex-DFFEX
    Info: Found entity 1: sld_dffex
Warning: Reduced register "reg16b:u2|dout[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "reg16b:u2|dout[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "reg16b:u2|dout[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "reg16b:u2|dout[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "reg16b:u2|dout[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "reg16b:u2|dout[0]" with stuck data_in port to stuck value GND
Info: Registers with preset signals will power-up high
Info: Implemented 211 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 9 output pins
    Info: Implemented 181 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Tue Jun 03 12:35:05 2008
    Info: Elapsed time: 00:00:05