📄 sin.map.rpt
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+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 116 ;
; Number of registers using Synchronous Clear ; 15 ;
; Number of registers using Synchronous Load ; 19 ;
; Number of registers using Asynchronous Clear ; 76 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 70 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; sld_hub:sld_hub_inst|hub_tdo ; 1 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |sin|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] ;
; 18:1 ; 4 bits ; 48 LEs ; 28 LEs ; 20 LEs ; Yes ; |sin|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sin|data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] ;
; 22:1 ; 4 bits ; 56 LEs ; 48 LEs ; 8 LEs ; Yes ; |sin|data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[2] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: data_rom:u3|altsyncram:altsyncram_component ;
+------------------------------------+---------------------------------------+----------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+---------------------------------------+----------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 8 ; Integer ;
; WIDTHAD_A ; 10 ; Integer ;
; NUMWORDS_A ; 1024 ; Integer ;
; OUTDATA_REG_A ; CLOCK0 ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; D:/altera/shiyan/sin/data/sin_rom.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_cfu ; Untyped ;
+------------------------------------+---------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2 ;
+-----------------------+------------+-------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+-----------------------+------------+-------------------------------------------------------------------------------------------------------------+
; sld_node_info ; 135818752 ; Integer ;
; sld_ip_version ; 1 ; Integer ;
; sld_ip_minor_version ; 0 ; Integer ;
; sld_common_ip_version ; 0 ; Integer ;
; width_word ; 8 ; Untyped ;
; numwords ; 1024 ; Untyped ;
; widthad ; 10 ; Untyped ;
; shift_count_bits ; 4 ; Untyped ;
; cvalue ; 00000000 ; Untyped ;
; is_data_in_ram ; 1 ; Untyped ;
; is_readable ; 1 ; Untyped ;
; node_name ; 1380928817 ; Untyped ;
+-----------------------+------------+-------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------+
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