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📄 sin.map.rpt

📁 基于Quartus II 5.0编写的正弦波发生器
💻 RPT
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; Maximum Number of M512 Memory Blocks                               ; -1           ; -1            ;
; Maximum Number of M4K Memory Blocks                                ; -1           ; -1            ;
; Maximum Number of M-RAM Memory Blocks                              ; -1           ; -1            ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off          ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                 ; On           ; On            ;
+--------------------------------------------------------------------+--------------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                              ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                    ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+
; sin.vhd                          ; yes             ; User VHDL File               ; D:/altera/shiyan/sin/sin.vhd                                                    ;
; reg16b.vhd                       ; yes             ; User VHDL File               ; D:/altera/shiyan/sin/reg16b.vhd                                                 ;
; adder16b.vhd                     ; yes             ; User VHDL File               ; D:/altera/shiyan/sin/adder16b.vhd                                               ;
; data_rom.vhd                     ; yes             ; User VHDL File               ; D:/altera/shiyan/sin/data_rom.vhd                                               ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; d:/program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/lpm_decode.inc        ;
; aglobal50.inc                    ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/aglobal50.inc         ;
; altsyncram.inc                   ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/altsyncram.inc        ;
; a_rdenreg.inc                    ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/altram.inc            ;
; altdpram.inc                     ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                     ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_cfu.tdf            ; yes             ; Auto-Generated Megafunction  ; D:/altera/shiyan/sin/db/altsyncram_cfu.tdf                                      ;
; db/altsyncram_aac2.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/altera/shiyan/sin/db/altsyncram_aac2.tdf                                     ;
; sld_mod_ram_rom.vhd              ; yes             ; Encrypted Megafunction       ; d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd   ;
; sld_rom_sr.vhd                   ; yes             ; Encrypted Megafunction       ; d:/program files/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd        ;
; sld_hub.vhd                      ; yes             ; Encrypted Megafunction       ; d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd           ;
; lpm_shiftreg.tdf                 ; yes             ; Megafunction                 ; d:/program files/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf      ;
; lpm_constant.inc                 ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/lpm_constant.inc      ;
; dffeea.inc                       ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/dffeea.inc            ;
; lpm_decode.tdf                   ; yes             ; Megafunction                 ; d:/program files/altera/quartus50/libraries/megafunctions/lpm_decode.tdf        ;
; declut.inc                       ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/declut.inc            ;
; altshift.inc                     ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/altshift.inc          ;
; lpm_compare.inc                  ; yes             ; Other                        ; d:/program files/altera/quartus50/libraries/megafunctions/lpm_compare.inc       ;
; db/decode_9ie.tdf                ; yes             ; Auto-Generated Megafunction  ; D:/altera/shiyan/sin/db/decode_9ie.tdf                                          ;
; sld_dffex.vhd                    ; yes             ; Encrypted Megafunction       ; d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd         ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+


+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                  ;
+-----------------------------------+--------------------------+
; Resource                          ; Usage                    ;
+-----------------------------------+--------------------------+
; Total logic elements              ; 181                      ;
; Total combinational functions     ; 150                      ;
;     -- Total 4-input functions    ; 40                       ;
;     -- Total 3-input functions    ; 52                       ;
;     -- Total 2-input functions    ; 34                       ;
;     -- Total 1-input functions    ; 24                       ;
;     -- Total 0-input functions    ; 0                        ;
; Combinational cells for routing   ; 0                        ;
; Total registers                   ; 116                      ;
; Total logic cells in carry chains ; 34                       ;
; I/O pins                          ; 17                       ;
; Total memory bits                 ; 8192                     ;
; Maximum fan-out node              ; altera_internal_jtag~TDO ;
; Maximum fan-out                   ; 120                      ;
; Total fan-out                     ; 959                      ;
; Average fan-out                   ; 4.55                     ;
+-----------------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                        ;
+---------------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                          ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                                                                                                         ;
+---------------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |sin                                                                ; 181 (0)     ; 116          ; 8192        ; 17   ; 0            ; 65 (0)       ; 31 (0)            ; 85 (0)           ; 34 (0)          ; |sin                                                                                                                                                        ;
;    |data_rom:u3|                                                    ; 65 (0)      ; 37           ; 8192        ; 0    ; 0            ; 28 (0)       ; 7 (0)             ; 30 (0)           ; 19 (0)          ; |sin|data_rom:u3                                                                                                                                            ;
;       |altsyncram:altsyncram_component|                             ; 65 (0)      ; 37           ; 8192        ; 0    ; 0            ; 28 (0)       ; 7 (0)             ; 30 (0)           ; 19 (0)          ; |sin|data_rom:u3|altsyncram:altsyncram_component                                                                                                            ;
;          |altsyncram_cfu:auto_generated|                            ; 65 (0)      ; 37           ; 8192        ; 0    ; 0            ; 28 (0)       ; 7 (0)             ; 30 (0)           ; 19 (0)          ; |sin|data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated                                                                              ;
;             |altsyncram_aac2:altsyncram1|                           ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |sin|data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1                                                  ;
;             |sld_mod_ram_rom:mgl_prim2|                             ; 65 (40)     ; 37           ; 0           ; 0    ; 0            ; 28 (12)      ; 7 (5)             ; 30 (23)          ; 19 (14)         ; |sin|data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2                                                    ;
;                |sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr| ; 25 (25)     ; 9            ; 0           ; 0    ; 0            ; 16 (16)      ; 2 (2)             ; 7 (7)            ; 5 (5)           ; |sin|data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr ;
;    |reg16b:u2|                                                      ; 10 (10)     ; 10           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 10 (10)          ; 10 (10)         ; |sin|reg16b:u2                                                                                                                                              ;
;    |sld_hub:sld_hub_inst|                                           ; 106 (28)    ; 69           ; 0           ; 0    ; 0            ; 37 (22)      ; 24 (1)            ; 45 (5)           ; 5 (0)           ; |sin|sld_hub:sld_hub_inst                                                                                                                                   ;
;       |lpm_decode:instruction_decoder|                              ; 5 (0)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (0)            ; 0 (0)           ; |sin|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder                                                                                                    ;
;          |decode_9ie:auto_generated|                                ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; 0 (0)           ; |sin|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated                                                                          ;
;       |lpm_shiftreg:jtag_ir_register|                               ; 10 (10)     ; 10           ; 0           ; 0    ; 0            ; 0 (0)        ; 10 (10)           ; 0 (0)            ; 0 (0)           ; |sin|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register                                                                                                     ;
;       |sld_dffex:BROADCAST|                                         ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |sin|sld_hub:sld_hub_inst|sld_dffex:BROADCAST                                                                                                               ;
;       |sld_dffex:IRF_ENA_0|                                         ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |sin|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0                                                                                                               ;
;       |sld_dffex:IRF_ENA|                                           ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |sin|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA                                                                                                                 ;
;       |sld_dffex:IRSR|                                              ; 8 (8)       ; 6            ; 0           ; 0    ; 0            ; 2 (2)        ; 1 (1)             ; 5 (5)            ; 0 (0)           ; |sin|sld_hub:sld_hub_inst|sld_dffex:IRSR                                                                                                                    ;
;       |sld_dffex:RESET|                                             ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |sin|sld_hub:sld_hub_inst|sld_dffex:RESET                                                                                                                   ;
;       |sld_dffex:\GEN_IRF:1:IRF|                                    ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; 0 (0)           ; |sin|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF                                                                                                          ;
;       |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|                           ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; 0 (0)           ; |sin|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF                                                                                                 ;
;       |sld_jtag_state_machine:jtag_state_machine|                   ; 21 (21)     ; 19           ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 19 (19)          ; 0 (0)           ; |sin|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine                                                                                         ;
;       |sld_rom_sr:HUB_INFO_REG|                                     ; 20 (20)     ; 9            ; 0           ; 0    ; 0            ; 11 (11)      ; 3 (3)             ; 6 (6)            ; 5 (5)           ; |sin|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG                                                                                                           ;
+---------------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                    ;
+------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+---------------------------------------+
; Name                                                                                                             ; Type ; Mode           ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF                                   ;
+------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+---------------------------------------+
; data_rom:u3|altsyncram:altsyncram_component|altsyncram_cfu:auto_generated|altsyncram_aac2:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 1024         ; 8            ; 1024         ; 8            ; 8192 ; D:/altera/shiyan/sin/data/sin_rom.mif ;
+------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+---------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;

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