add_rounding.mdl

一个基于Matlab+Simulink的带Rounding功能的加法器实现

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	      SFDataObjDesc	      off
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	      PrefixModelToSubsysFcnNames on
	      CustomSymbolStr	      "$R$N$M"
	      MangleLength	      1
	      DefineNamingRule	      "None"
	      ParamNamingRule	      "None"
	      SignalNamingRule	      "None"
	      InsertBlockDesc	      off
	      SimulinkBlockComments   on
	      EnableCustomComments    off
	      InlinedPrmAccess	      "Literals"
	      ReqsInCode	      off
	    }
	    Simulink.GRTTargetCC {
	      $BackupClass	      "Simulink.TargetCC"
	      $ObjectID		      10
	      Array {
		Type			"Cell"
		Dimension		12
		Cell			"IncludeMdlTerminateFcn"
		Cell			"CombineOutputUpdateFcns"
		Cell			"SuppressErrorStatus"
		Cell			"ERTCustomFileBanners"
		Cell			"GenerateSampleERTMain"
		Cell			"MultiInstanceERTCode"
		Cell			"PurelyIntegerCode"
		Cell			"SupportNonFinite"
		Cell			"SupportComplex"
		Cell			"SupportAbsoluteTime"
		Cell			"SupportContinuousTime"
		Cell			"SupportNonInlinedSFcns"
		PropName		"DisabledProps"
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	      Version		      "1.1.0"
	      TargetFcnLib	      "ansi_tfl_tmw.mat"
	      TargetLibSuffix	      ""
	      TargetPreCompLibLocation ""
	      GenFloatMathFcnCalls    "ANSI_C"
	      UtilityFuncGeneration   "Auto"
	      GenerateFullHeader      on
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	      IsPILTarget	      off
	      ModelReferenceCompliant on
	      IncludeMdlTerminateFcn  on
	      CombineOutputUpdateFcns off
	      SuppressErrorStatus     off
	      IncludeFileDelimiter    "Auto"
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	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
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	      SupportContinuousTime   on
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	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
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      SimulationMode	      "normal"
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    PropName		    "ConfigurationSets"
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  Simulink.ConfigSet {
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  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      DiscretePulseGenerator
      PulseType		      "Sample based"
      TimeSource	      "Use simulation time"
      Amplitude		      "1"
      Period		      "2"
      PulseWidth	      "1"
      PhaseDelay	      "0"
      SampleTime	      "1"
      VectorParams1D	      on
    }
    Block {
      BlockType		      Scope
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      ModelBased	      off
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      YMin		      "-5"
      YMax		      "5"
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      SaveName		      "ScopeData"
      LimitDataPoints	      on
      MaxDataPoints	      "5000"
      Decimation	      "1"
      SampleInput	      off
      SampleTime	      "0"
    }
    Block {
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    Block {
      BlockType		      SubSystem
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      PermitHierarchicalResolution "All"
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Terminator
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "add_rounding"
    Location		    [105, 112, 885, 656]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
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      ShowPortLabels	      on
      xilinxfamily	      "Virtex2"
      part		      "xc2v40"
      speed		      "-4"
      package		      "cs144"
      synthesis_tool	      "XST"
      directory		      "./netlist"
      testbench		      off
      simulink_period	      "1"
      sysclk_period	      "100"
      incr_netlist	      off
      trim_vbits	      "Everywhere in SubSystem"
      dbl_ovrd		      "According to Block Masks"
      core_generation	      "According to Block Masks"
      run_coregen	      off
      deprecated_control      off
      eval_field	      "0"
      block_type	      "sysgen"
    }
    Block {
      BlockType		      Sum
      Name		      "Add1"
      Ports		      [2, 1]
      Position		      [560, 172, 590, 203]
      Inputs		      "+-"
      InputSameDT	      off
      OutDataTypeMode	      "Inherit via internal rule"
      OutScaling	      "2^-10"
      SaturateOnIntegerOverflow	off
    }
    Block {
      BlockType		      Sum
      Name		      "Add2"
      Ports		      [2, 1]
      Position		      [560, 307, 590, 338]
      Inputs		      "+-"
      InputSameDT	      off
      OutDataTypeMode	      "Inherit via internal rule"
      OutScaling	      "2^-10"
      SaturateOnIntegerOverflow	off
    }
    Block {
      BlockType		      Sum
      Name		      "Add3"
      Ports		      [2, 1]
      Position		      [560, 442, 590, 473]
      Inputs		      "+-"
      InputSameDT	      off
      OutDataTypeMode	      "Inherit via internal rule"
      OutScaling	      "2^-10"
      SaturateOnIntegerOverflow	off
    }
    Block {
      BlockType		      Sum
      Name		      "Add4"
      Ports		      [2, 1]
      Position		      [355, 56, 385, 89]
      InputSameDT	      off
      OutDataTypeMode	      "double"
      OutScaling	      "2^-10"
      SaturateOnIntegerOverflow	off
    }
    Block {
      BlockType		      Reference
      Name		      "AddSub"
      Ports		      [2, 1]
      Position		      [345, 167, 395, 218]
      SourceBlock	      "xbsIndex_r4/AddSub"
      SourceType	      "Xilinx Adder/Subtractor Block"
      mode		      "Addition"
      use_carryin	      off
      use_carryout	      off
      en		      off
      latency		      "0"
      precision		      "User Defined"
      arith_type	      "Signed  (2's comp)"
      n_bits		      "17"
      bin_pt		      "15"
      quantization	      "Truncate"
      overflow		      "Wrap"
      dbl_ovrd		      off
      use_behavioral_HDL      on
      pipelined		      off
      use_rpm		      on
      xl_use_area	      off
      xl_area		      "[0, 0, 0, 0, 0, 0, 0]"
      block_version	      "VER_STRING_GOES_HERE"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "addsub"
      sg_icon_stat	      "50,51,2,1,white,blue,0,84d1e665"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 "
"32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 "
"38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 50 50 0 ],[0 51 51 0"
" 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: beg"
"in icon text ');\ncolor('black');port_label('input',1,'a');\ncolor('black');p"
"ort_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'"
",'texmode','on');\nfprintf('','COMMENT: end icon text');\n"
    }
    Block {
      BlockType		      Reference
      Name		      "AddSub1"
      Ports		      [2, 1]
      Position		      [345, 302, 395, 353]
      SourceBlock	      "xbsIndex_r4/AddSub"
      SourceType	      "Xilinx Adder/Subtractor Block"
      mode		      "Addition"
      use_carryin	      off
      use_carryout	      off
      en		      off
      latency		      "0"
      precision		      "User Defined"
      arith_type	      "Signed  (2's comp)"
      n_bits		      "6"
      bin_pt		      "4"
      quantization	      "Truncate"
      overflow		      "Wrap"
      dbl_ovrd		      off
      use_behavioral_HDL      on
      pipelined		      off