add_rounding.mdl
来自「一个基于Matlab+Simulink的带Rounding功能的加法器实现」· MDL 代码 · 共 1,322 行 · 第 1/4 页
MDL
1,322 行
use_rpm on
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "addsub"
sg_icon_stat "50,51,2,1,white,blue,0,84d1e665"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 "
"32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 "
"38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 50 50 0 ],[0 51 51 0"
" 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: beg"
"in icon text ');\ncolor('black');port_label('input',1,'a');\ncolor('black');p"
"ort_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'"
",'texmode','on');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "AddSub2"
Ports [2, 1]
Position [345, 437, 395, 488]
SourceBlock "xbsIndex_r4/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
use_carryin off
use_carryout off
en off
latency "0"
precision "User Defined"
arith_type "Signed (2's comp)"
n_bits "6"
bin_pt "4"
quantization "Round (unbiased: +/- Inf)"
overflow "Wrap"
dbl_ovrd off
use_behavioral_HDL on
pipelined off
use_rpm on
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "addsub"
sg_icon_stat "50,51,2,1,white,blue,0,84d1e665"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 "
"32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 "
"38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 50 50 0 ],[0 51 51 0"
" 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: beg"
"in icon text ');\ncolor('black');port_label('input',1,'a');\ncolor('black');p"
"ort_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'"
",'texmode','on');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Gateway In"
Ports [1, 1]
Position [100, 294, 155, 316]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Signed (2's comp)"
n_bits "16"
bin_pt "15"
quantization "Round (unbiased: +/- Inf)"
overflow "Wrap"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "20,20,356,414"
block_type "gatewayin"
sg_icon_stat "55,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In "
"','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','C"
"OMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this lin"
"e -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Gateway In1"
Ports [1, 1]
Position [100, 359, 155, 381]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Signed (2's comp)"
n_bits "16"
bin_pt "15"
quantization "Round (unbiased: +/- Inf)"
overflow "Wrap"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayin"
sg_icon_stat "55,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In "
"','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','C"
"OMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this lin"
"e -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Gateway Out"
Ports [1, 1]
Position [455, 184, 510, 206]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed point"
" inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Ha"
"rdware notes: In hardware these blocks become top level output ports or are "
"discarded, depending on how they are configured."
hdl_port on
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "20,20,356,327"
block_type "gatewayout"
sg_icon_stat "55,22,1,1,white,yellow,0,f0cec300"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,' ');\ncolor('black');por"
"t_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','"
"COMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this li"
"ne -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Gateway Out1"
Ports [1, 1]
Position [455, 319, 510, 341]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed point"
" inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Ha"
"rdware notes: In hardware these blocks become top level output ports or are "
"discarded, depending on how they are configured."
hdl_port on
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayout"
sg_icon_stat "55,22,1,1,white,yellow,0,f0cec300"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,' ');\ncolor('black');por"
"t_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','"
"COMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this li"
"ne -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Gateway Out2"
Ports [1, 1]
Position [455, 454, 510, 476]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed point"
" inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Ha"
"rdware notes: In hardware these blocks become top level output ports or are "
"discarded, depending on how they are configured."
hdl_port on
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayout"
sg_icon_stat "55,22,1,1,white,yellow,0,f0cec300"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,' ');\ncolor('black');por"
"t_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','"
"COMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this li"
"ne -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Gateway Out3"
Ports [1, 1]
Position [195, 39, 250, 61]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed point"
" inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Ha"
"rdware notes: In hardware these blocks become top level output ports or are "
"discarded, depending on how they are configured."
hdl_port off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayout"
sg_icon_stat "55,22,1,1,white,grey,0,422cd57d"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.88 0.88 0.88]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,' ');\ncolor('black');por"
"t_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMM"
"ENT: end icon text');\nfprintf('','COMMENT: Make no changes above this line -"
"- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Gateway Out4"
Ports [1, 1]
Position [195, 84, 250, 106]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed point"
" inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Ha"
"rdware notes: In hardware these blocks become top level output ports or are "
"discarded, depending on how they are configured."
hdl_port off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "20,20,356,327"
block_type "gatewayout"
sg_icon_stat "55,22,1,1,white,grey,0,422cd57d"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.88 0.88 0.88]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,' ');\ncolor('black');por"
"t_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMM"
"ENT: end icon text');\nfprintf('','COMMENT: Make no changes above this line -"
"- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Random\nSource"
Ports [0, 1]
Position [35, 286, 70, 324]
UserDataPersistent on
UserData "DataTag1"
Diagnostics "AllowInheritedTsInSrc"
SourceBlock "dspsrcs4/Random\nSource"
SourceType "Random Source"
SrcType "Uniform"
NormMethod "Ziggurat"
CltLength "12"
MinVal "-1"
MaxVal "1"
MeanVal "0"
VarVal "1"
RepMode "Not repeatable"
rawSeed "1"
IsInherit off
SampMode "Discrete"
SampTime "1"
SampFrame "1"
DataType "Double"
OutComplex "Real"
}
Block {
BlockType Reference
Name "Random\nSource1"
Ports [0, 1]
Position [35, 351, 70, 389]
UserDataPersistent on
UserData "DataTag2"
Diagnostics "AllowInheritedTsInSrc"
SourceBlock "dspsrcs4/Random\nSource"
SourceType "Random Source"
SrcType "Uniform"
NormMethod "Ziggurat"
CltLength "12"
MinVal "-1"
MaxVal "1"
MeanVal "0"
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