📄 add_overflow.mdl
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Cell "DefineNamingRule"
Cell "SignalNamingRule"
Cell "ParamNamingRule"
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Cell "CustomSymbolStr"
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}
Version "1.1.0"
ForceParamTrailComments off
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IgnoreCustomStorageClasses on
IncHierarchyInIds off
MaxIdLength 31
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IncAutoGenComments off
SimulinkDataObjDesc off
SFDataObjDesc off
IncDataTypeInIds off
PrefixModelToSubsysFcnNames on
CustomSymbolStr "$R$N$M"
MangleLength 1
DefineNamingRule "None"
ParamNamingRule "None"
SignalNamingRule "None"
InsertBlockDesc off
SimulinkBlockComments on
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InlinedPrmAccess "Literals"
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Simulink.GRTTargetCC {
$BackupClass "Simulink.TargetCC"
$ObjectID 10
Array {
Type "Cell"
Dimension 12
Cell "IncludeMdlTerminateFcn"
Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportNonFinite"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
PropName "DisabledProps"
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Version "1.1.0"
TargetFcnLib "ansi_tfl_tmw.mat"
TargetLibSuffix ""
TargetPreCompLibLocation ""
GenFloatMathFcnCalls "ANSI_C"
UtilityFuncGeneration "Auto"
GenerateFullHeader on
GenerateSampleERTMain off
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IncludeMdlTerminateFcn on
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IncludeFileDelimiter "Auto"
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ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
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}
PropName "Components"
}
Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
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PropName "ConfigurationSets"
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Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
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BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
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BlockParameterDefaults {
Block {
BlockType Constant
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VectorParams1D on
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
}
Block {
BlockType DiscretePulseGenerator
PulseType "Sample based"
TimeSource "Use simulation time"
Amplitude "1"
Period "2"
PulseWidth "1"
PhaseDelay "0"
SampleTime "1"
VectorParams1D on
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Block {
BlockType Display
Format "short"
Decimation "10"
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SampleTime "-1"
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Block {
BlockType "S-Function"
FunctionName "system"
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PortCounts "[]"
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BlockType SubSystem
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MinMaxOverflowLogging "UseLocalSettings"
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Block {
BlockType Terminator
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AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
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FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "add_overflow"
Location [188, 100, 1006, 703]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name " System Generator"
Tag "genX"
Ports []
Position [37, 33, 88, 83]
ShowName off
AttributesFormatString "System\\nGenerator"
UserDataPersistent on
UserData "DataTag0"
SourceBlock "xbsIndex_r4/ System Generator"
SourceType "Xilinx System Generator"
ShowPortLabels on
xilinxfamily "Virtex2"
part "xc2v40"
speed "-4"
package "cs144"
synthesis_tool "XST"
directory "./netlist"
testbench off
simulink_period "1"
sysclk_period "100"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
block_type "sysgen"
}
Block {
BlockType Reference
Name "AddSub"
Ports [2, 1]
Position [340, 67, 390, 118]
SourceBlock "xbsIndex_r4/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
use_carryin off
use_carryout off
en off
latency "0"
precision "User Defined"
arith_type "Signed (2's comp)"
n_bits "4"
bin_pt "0"
quantization "Truncate"
overflow "Wrap"
dbl_ovrd off
use_behavioral_HDL on
pipelined off
use_rpm on
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "addsub"
sg_icon_stat "50,51,2,1,white,blue,0,84d1e665"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 "
"32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 "
"38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 50 50 0 ],[0 51 51 0"
" 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: beg"
"in icon text ');\ncolor('black');port_label('input',1,'a');\ncolor('black');p"
"ort_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'"
",'texmode','on');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "AddSub1"
Ports [2, 1]
Position [340, 252, 390, 303]
SourceBlock "xbsIndex_r4/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
use_carryin off
use_carryout off
en off
latency "0"
precision "User Defined"
arith_type "Signed (2's comp)"
n_bits "4"
bin_pt "0"
quantization "Truncate"
overflow "Saturate"
dbl_ovrd off
use_behavioral_HDL on
pipelined off
use_rpm on
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "addsub"
sg_icon_stat "50,51,2,1,white,blue,0,84d1e665"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 "
"32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 "
"38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 50 50 0 ],[0 51 51 0"
" 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: beg"
"in icon text ');\ncolor('black');port_label('input',1,'a');\ncolor('black');p"
"ort_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'"
",'texmode','on');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "AddSub2"
Ports [2, 1]
Position [340, 442, 390, 493]
SourceBlock "xbsIndex_r4/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
use_carryin off
use_carryout off
en off
latency "0"
precision "User Defined"
arith_type "Signed (2's comp)"
n_bits "5"
bin_pt "0"
quantization "Truncate"
overflow "Wrap"
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