test.v

一个简单状态机的.v文件

`timescale 1ns / 10ps
module test;
	reg sys_clk;
	reg sys_rst;
	reg sys_A;
	reg sys_B;
	
	wire [1:0]out_A;
	wire out_B;
	
	machine st(sys_A,sys_B,sys_clk,sys_rst,out_A,out_B);

	initial
		begin
			$dumpfile("test_out.fsdb");
			$dumpvars;
		end
	
	initial begin
    sys_rst = 1;
    sys_clk = 0;
    sys_A = 0;
    sys_B = 0;
    #110;
    sys_rst = 0;
    #100;
    sys_rst = 1;
    #100;
    sys_A = 1;
    #100;
    sys_B = 1;
    #100;
    sys_B = 0;
    #100;
    sys_B = 1;
    #100;
    sys_A = 0;
    sys_B = 0;
    #100;
    sys_A = 0;
    #100;
    sys_B = 1;
    #100;
    sys_rst = 0;
    #200;
    sys_A = 1;
    #100;
    sys_rst = 1;
    #100;
    sys_A = 0;   
    sys_B = 0; 
	
	end
  always #40 sys_clk=~sys_clk;   
  
  initial
  #2000 $finish;
endmodule