machine.v

来自「一个简单状态机的.v文件」· Verilog 代码 · 共 76 行

`timescale 1ns/10ps
module machine(
				//input
				A,
				B,
				clk,
				rst_n,
				//output
				outA,
				outB
				);
input A,B,clk,rst_n;
output [1:0]outA;
output outB;
reg [1:0]outA_t;
reg outB_t;

assign outA=outA_t;
assign outB=outB_t;

parameter [4:0]
								IDLE	 =	 5'd0,
								S1		=	5'd1,
								S2		=	5'd2,
								S3		=	5'd3,
								S4		=	5'd4;

reg[4:0] state, next;

always@(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
								state <= 5'b0;
								state[IDLE] <= 1'b1;
							end								
	else					state <= next;
end
	
always@(state or A or B) begin
	next = 5'b0;
	outA_t<=2'b00;
	outB_t<=1'b0;
	case(1'b1)
	state[IDLE]:	begin							
					next[S1]=1'b1;
					outA_t<=2'b00;
					outB_t<=1'b0;
				end
	state[S1]:		begin
					if (A==1 && B==1)		next[S2]=1'b1;
					else if (A==0 && B==0)		next[S3]=1'b1;
					else								next[S1]=1'b1;
					outA_t<=2'b10;
					outB_t<=1'b1;
				end
	state[S2]:		begin		
					if (A==1 && B==0)		next[S3]=1'b1;
					else								next[S2]=1'b1;
					outA_t<=2'b01;
					outB_t<=1'b0;
				end
	state[S3]:		begin
					if (A==0 && B==0)		next[S4]=1'b1;
					else 								next[S3]=1'b1;
					outA_t<=2'b00;
					outB_t<=1'b1;
				end
	state[S4]:		begin
					if (A==1 && B==0)		next[S1]=1'b1;
					else if (A==0 && B==1)		next[S2]=1'b1;
					else 								next[S4]=1'b1;
					outA_t<=2'b11;
					outB_t<=1'b0;
				end
	endcase
end
endmodule