prev_cmp_clock_div.qmsg

除頻code,只要修改數字並接上時脈,即可得到所要的頻率

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 02 15:31:02 2008 " "Info: Processing started: Fri May 02 15:31:02 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock_div -c clock_div --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock_div -c clock_div --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_div.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock_div.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_div " "Info: Found entity 1: clock_div" {  } { { "clock_div.v" "" { Text "D:/NKFUST/FPGA/ALTERA/myFPGA/DIV_CLK/clock_div.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock_div " "Info: Elaborating entity \"clock_div\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 clock_div.v(9) " "Warning (10230): Verilog HDL assignment warning at clock_div.v(9): truncated value with size 32 to match size of target (20)" {  } { { "clock_div.v" "" { Text "D:/NKFUST/FPGA/ALTERA/myFPGA/DIV_CLK/clock_div.v" 9 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 clock_div.v(15) " "Warning (10230): Verilog HDL assignment warning at clock_div.v(15): truncated value with size 32 to match size of target (20)" {  } { { "clock_div.v" "" { Text "D:/NKFUST/FPGA/ALTERA/myFPGA/DIV_CLK/clock_div.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 2 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "154 " "Info: Allocated 154 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 02 15:31:03 2008 " "Info: Processing ended: Fri May 02 15:31:03 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}