clock_div.v

来自「除頻code,只要修改數字並接上時脈,即可得到所要的頻率」· Verilog 代码 · 共 22 行

module clock_div(oclk,iclk);
	output reg oclk;
	input iclk;
	reg [19:0]counter1 = 0;
	always@(posedge iclk )
	begin
		if(counter1<3)//div n
		begin
		counter1=counter1+1;
		oclk=iclk;
		end
		else if(counter1>=3)//div n		
		begin
			oclk = ~iclk;
			counter1=counter1+1;
			if(counter1>=6)//n*2
			begin
			counter1 = 0;
			end
		end
	end
endmodule