clock_div.sim.rpt

除頻code,只要修改數字並接上時脈,即可得到所要的頻率

; |clock_div|Add0~117     ; |clock_div|Add0~117     ; out0             ;
; |clock_div|Add0~118     ; |clock_div|Add0~118     ; out0             ;
; |clock_div|Add0~119     ; |clock_div|Add0~119     ; out0             ;
; |clock_div|Add0~120     ; |clock_div|Add0~120     ; out0             ;
; |clock_div|Add0~121     ; |clock_div|Add0~121     ; out0             ;
; |clock_div|Add0~122     ; |clock_div|Add0~122     ; out0             ;
; |clock_div|Add0~123     ; |clock_div|Add0~123     ; out0             ;
; |clock_div|Add0~124     ; |clock_div|Add0~124     ; out0             ;
; |clock_div|Add0~125     ; |clock_div|Add0~125     ; out0             ;
; |clock_div|Add0~126     ; |clock_div|Add0~126     ; out0             ;
; |clock_div|Add0~127     ; |clock_div|Add0~127     ; out0             ;
; |clock_div|Add0~128     ; |clock_div|Add0~128     ; out0             ;
; |clock_div|Add0~129     ; |clock_div|Add0~129     ; out0             ;
; |clock_div|Add0~130     ; |clock_div|Add0~130     ; out0             ;
; |clock_div|Add0~131     ; |clock_div|Add0~131     ; out0             ;
; |clock_div|Add0~132     ; |clock_div|Add0~132     ; out0             ;
; |clock_div|Add0~133     ; |clock_div|Add0~133     ; out0             ;
; |clock_div|Add0~134     ; |clock_div|Add0~134     ; out0             ;
; |clock_div|Add0~135     ; |clock_div|Add0~135     ; out0             ;
; |clock_div|Add0~136     ; |clock_div|Add0~136     ; out0             ;
+-------------------------+-------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------+
; Missing 0-Value Coverage                                             ;
+-------------------------+-------------------------+------------------+
; Node Name               ; Output Port Name        ; Output Port Type ;
+-------------------------+-------------------------+------------------+
; |clock_div|counter1~0   ; |clock_div|counter1~0   ; out              ;
; |clock_div|counter1~1   ; |clock_div|counter1~1   ; out              ;
; |clock_div|counter1~2   ; |clock_div|counter1~2   ; out              ;
; |clock_div|counter1~3   ; |clock_div|counter1~3   ; out              ;
; |clock_div|counter1~4   ; |clock_div|counter1~4   ; out              ;
; |clock_div|counter1~5   ; |clock_div|counter1~5   ; out              ;
; |clock_div|counter1~6   ; |clock_div|counter1~6   ; out              ;
; |clock_div|counter1~7   ; |clock_div|counter1~7   ; out              ;
; |clock_div|counter1~8   ; |clock_div|counter1~8   ; out              ;
; |clock_div|counter1~9   ; |clock_div|counter1~9   ; out              ;
; |clock_div|counter1~10  ; |clock_div|counter1~10  ; out              ;
; |clock_div|counter1~11  ; |clock_div|counter1~11  ; out              ;
; |clock_div|counter1~12  ; |clock_div|counter1~12  ; out              ;
; |clock_div|counter1~13  ; |clock_div|counter1~13  ; out              ;
; |clock_div|counter1~14  ; |clock_div|counter1~14  ; out              ;
; |clock_div|counter1~15  ; |clock_div|counter1~15  ; out              ;
; |clock_div|counter1~20  ; |clock_div|counter1~20  ; out              ;
; |clock_div|counter1~21  ; |clock_div|counter1~21  ; out              ;
; |clock_div|counter1~22  ; |clock_div|counter1~22  ; out              ;
; |clock_div|counter1~23  ; |clock_div|counter1~23  ; out              ;
; |clock_div|counter1~24  ; |clock_div|counter1~24  ; out              ;
; |clock_div|counter1~25  ; |clock_div|counter1~25  ; out              ;
; |clock_div|counter1~26  ; |clock_div|counter1~26  ; out              ;
; |clock_div|counter1~27  ; |clock_div|counter1~27  ; out              ;
; |clock_div|counter1~28  ; |clock_div|counter1~28  ; out              ;
; |clock_div|counter1~29  ; |clock_div|counter1~29  ; out              ;
; |clock_div|counter1~30  ; |clock_div|counter1~30  ; out              ;
; |clock_div|counter1~31  ; |clock_div|counter1~31  ; out              ;
; |clock_div|counter1~32  ; |clock_div|counter1~32  ; out              ;
; |clock_div|counter1~33  ; |clock_div|counter1~33  ; out              ;
; |clock_div|counter1~34  ; |clock_div|counter1~34  ; out              ;
; |clock_div|counter1~35  ; |clock_div|counter1~35  ; out              ;
; |clock_div|counter1~40  ; |clock_div|counter1~40  ; out              ;
; |clock_div|counter1~41  ; |clock_div|counter1~41  ; out              ;
; |clock_div|counter1~42  ; |clock_div|counter1~42  ; out              ;
; |clock_div|counter1~43  ; |clock_div|counter1~43  ; out              ;
; |clock_div|counter1~44  ; |clock_div|counter1~44  ; out              ;
; |clock_div|counter1~45  ; |clock_div|counter1~45  ; out              ;
; |clock_div|counter1~46  ; |clock_div|counter1~46  ; out              ;
; |clock_div|counter1~47  ; |clock_div|counter1~47  ; out              ;
; |clock_div|counter1~48  ; |clock_div|counter1~48  ; out              ;
; |clock_div|counter1~49  ; |clock_div|counter1~49  ; out              ;
; |clock_div|counter1~50  ; |clock_div|counter1~50  ; out              ;
; |clock_div|counter1~51  ; |clock_div|counter1~51  ; out              ;
; |clock_div|counter1~52  ; |clock_div|counter1~52  ; out              ;
; |clock_div|counter1~53  ; |clock_div|counter1~53  ; out              ;
; |clock_div|counter1~54  ; |clock_div|counter1~54  ; out              ;
; |clock_div|counter1~55  ; |clock_div|counter1~55  ; out              ;
; |clock_div|counter1[3]  ; |clock_div|counter1[3]  ; regout           ;
; |clock_div|counter1[4]  ; |clock_div|counter1[4]  ; regout           ;
; |clock_div|counter1[5]  ; |clock_div|counter1[5]  ; regout           ;
; |clock_div|counter1[6]  ; |clock_div|counter1[6]  ; regout           ;
; |clock_div|counter1[7]  ; |clock_div|counter1[7]  ; regout           ;
; |clock_div|counter1[8]  ; |clock_div|counter1[8]  ; regout           ;
; |clock_div|counter1[9]  ; |clock_div|counter1[9]  ; regout           ;
; |clock_div|counter1[10] ; |clock_div|counter1[10] ; regout           ;
; |clock_div|counter1[11] ; |clock_div|counter1[11] ; regout           ;
; |clock_div|counter1[12] ; |clock_div|counter1[12] ; regout           ;
; |clock_div|counter1[13] ; |clock_div|counter1[13] ; regout           ;
; |clock_div|counter1[14] ; |clock_div|counter1[14] ; regout           ;
; |clock_div|counter1[15] ; |clock_div|counter1[15] ; regout           ;
; |clock_div|counter1[16] ; |clock_div|counter1[16] ; regout           ;
; |clock_div|counter1[17] ; |clock_div|counter1[17] ; regout           ;
; |clock_div|counter1[18] ; |clock_div|counter1[18] ; regout           ;
; |clock_div|counter1[19] ; |clock_div|counter1[19] ; regout           ;
; |clock_div|Add0~105     ; |clock_div|Add0~105     ; out0             ;
; |clock_div|Add0~106     ; |clock_div|Add0~106     ; out0             ;
; |clock_div|Add0~107     ; |clock_div|Add0~107     ; out0             ;
; |clock_div|Add0~108     ; |clock_div|Add0~108     ; out0             ;
; |clock_div|Add0~109     ; |clock_div|Add0~109     ; out0             ;
; |clock_div|Add0~110     ; |clock_div|Add0~110     ; out0             ;
; |clock_div|Add0~111     ; |clock_div|Add0~111     ; out0             ;
; |clock_div|Add0~112     ; |clock_div|Add0~112     ; out0             ;
; |clock_div|Add0~113     ; |clock_div|Add0~113     ; out0             ;
; |clock_div|Add0~114     ; |clock_div|Add0~114     ; out0             ;
; |clock_div|Add0~115     ; |clock_div|Add0~115     ; out0             ;
; |clock_div|Add0~116     ; |clock_div|Add0~116     ; out0             ;
; |clock_div|Add0~117     ; |clock_div|Add0~117     ; out0             ;
; |clock_div|Add0~118     ; |clock_div|Add0~118     ; out0             ;
; |clock_div|Add0~119     ; |clock_div|Add0~119     ; out0             ;
; |clock_div|Add0~120     ; |clock_div|Add0~120     ; out0             ;
; |clock_div|Add0~121     ; |clock_div|Add0~121     ; out0             ;
; |clock_div|Add0~122     ; |clock_div|Add0~122     ; out0             ;
; |clock_div|Add0~123     ; |clock_div|Add0~123     ; out0             ;
; |clock_div|Add0~124     ; |clock_div|Add0~124     ; out0             ;
; |clock_div|Add0~125     ; |clock_div|Add0~125     ; out0             ;
; |clock_div|Add0~126     ; |clock_div|Add0~126     ; out0             ;
; |clock_div|Add0~127     ; |clock_div|Add0~127     ; out0             ;
; |clock_div|Add0~128     ; |clock_div|Add0~128     ; out0             ;
; |clock_div|Add0~129     ; |clock_div|Add0~129     ; out0             ;
; |clock_div|Add0~130     ; |clock_div|Add0~130     ; out0             ;
; |clock_div|Add0~131     ; |clock_div|Add0~131     ; out0             ;
; |clock_div|Add0~132     ; |clock_div|Add0~132     ; out0             ;
; |clock_div|Add0~133     ; |clock_div|Add0~133     ; out0             ;
; |clock_div|Add0~134     ; |clock_div|Add0~134     ; out0             ;
; |clock_div|Add0~135     ; |clock_div|Add0~135     ; out0             ;
; |clock_div|Add0~136     ; |clock_div|Add0~136     ; out0             ;
+-------------------------+-------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Jun 04 21:05:54 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off clock_div -c clock_div
Info: Using vector source file "D:/NKFUST/FPGA/ALTERA/myFPGA/DIV_CLK/clock_div.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      54.67 %
Info: Number of transitions in simulation is 6787
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 116 megabytes of memory during processing
    Info: Processing ended: Wed Jun 04 21:05:55 2008
    Info: Elapsed time: 00:00:01