clock_div.sim.rpt

除頻code,只要修改數字並接上時脈,即可得到所要的頻率

; |clock_div|LessThan1~86  ; |clock_div|LessThan1~86  ; out0             ;
; |clock_div|LessThan1~87  ; |clock_div|LessThan1~87  ; out0             ;
; |clock_div|LessThan1~88  ; |clock_div|LessThan1~88  ; out0             ;
; |clock_div|LessThan1~89  ; |clock_div|LessThan1~89  ; out0             ;
; |clock_div|LessThan1~90  ; |clock_div|LessThan1~90  ; out0             ;
; |clock_div|LessThan1~91  ; |clock_div|LessThan1~91  ; out0             ;
; |clock_div|LessThan1~92  ; |clock_div|LessThan1~92  ; out0             ;
; |clock_div|LessThan1~93  ; |clock_div|LessThan1~93  ; out0             ;
; |clock_div|LessThan1~94  ; |clock_div|LessThan1~94  ; out0             ;
; |clock_div|LessThan1~95  ; |clock_div|LessThan1~95  ; out0             ;
; |clock_div|LessThan1~96  ; |clock_div|LessThan1~96  ; out0             ;
; |clock_div|LessThan1~97  ; |clock_div|LessThan1~97  ; out0             ;
; |clock_div|LessThan1~98  ; |clock_div|LessThan1~98  ; out0             ;
; |clock_div|LessThan1~99  ; |clock_div|LessThan1~99  ; out0             ;
; |clock_div|LessThan1~100 ; |clock_div|LessThan1~100 ; out0             ;
; |clock_div|LessThan1~101 ; |clock_div|LessThan1~101 ; out0             ;
; |clock_div|LessThan1~102 ; |clock_div|LessThan1~102 ; out0             ;
; |clock_div|LessThan1~103 ; |clock_div|LessThan1~103 ; out0             ;
; |clock_div|LessThan1~104 ; |clock_div|LessThan1~104 ; out0             ;
; |clock_div|LessThan1~105 ; |clock_div|LessThan1~105 ; out0             ;
; |clock_div|LessThan1~106 ; |clock_div|LessThan1~106 ; out0             ;
; |clock_div|LessThan1~107 ; |clock_div|LessThan1~107 ; out0             ;
; |clock_div|LessThan1~108 ; |clock_div|LessThan1~108 ; out0             ;
; |clock_div|LessThan1~109 ; |clock_div|LessThan1~109 ; out0             ;
; |clock_div|LessThan1~110 ; |clock_div|LessThan1~110 ; out0             ;
; |clock_div|LessThan1~111 ; |clock_div|LessThan1~111 ; out0             ;
; |clock_div|LessThan1~112 ; |clock_div|LessThan1~112 ; out0             ;
; |clock_div|LessThan1~113 ; |clock_div|LessThan1~113 ; out0             ;
; |clock_div|LessThan1~114 ; |clock_div|LessThan1~114 ; out0             ;
; |clock_div|LessThan1~115 ; |clock_div|LessThan1~115 ; out0             ;
; |clock_div|LessThan1~116 ; |clock_div|LessThan1~116 ; out0             ;
; |clock_div|LessThan2~80  ; |clock_div|LessThan2~80  ; out0             ;
; |clock_div|LessThan2~81  ; |clock_div|LessThan2~81  ; out0             ;
; |clock_div|LessThan2~82  ; |clock_div|LessThan2~82  ; out0             ;
; |clock_div|LessThan2~83  ; |clock_div|LessThan2~83  ; out0             ;
; |clock_div|LessThan2~84  ; |clock_div|LessThan2~84  ; out0             ;
; |clock_div|LessThan2~85  ; |clock_div|LessThan2~85  ; out0             ;
; |clock_div|LessThan2~86  ; |clock_div|LessThan2~86  ; out0             ;
; |clock_div|LessThan2~87  ; |clock_div|LessThan2~87  ; out0             ;
; |clock_div|LessThan2~88  ; |clock_div|LessThan2~88  ; out0             ;
; |clock_div|LessThan2~89  ; |clock_div|LessThan2~89  ; out0             ;
; |clock_div|LessThan2~90  ; |clock_div|LessThan2~90  ; out0             ;
; |clock_div|LessThan2~91  ; |clock_div|LessThan2~91  ; out0             ;
; |clock_div|LessThan2~92  ; |clock_div|LessThan2~92  ; out0             ;
; |clock_div|LessThan2~93  ; |clock_div|LessThan2~93  ; out0             ;
; |clock_div|LessThan2~94  ; |clock_div|LessThan2~94  ; out0             ;
; |clock_div|LessThan2~95  ; |clock_div|LessThan2~95  ; out0             ;
; |clock_div|LessThan2~96  ; |clock_div|LessThan2~96  ; out0             ;
; |clock_div|LessThan2~97  ; |clock_div|LessThan2~97  ; out0             ;
; |clock_div|LessThan2~98  ; |clock_div|LessThan2~98  ; out0             ;
; |clock_div|LessThan2~99  ; |clock_div|LessThan2~99  ; out0             ;
; |clock_div|LessThan2~100 ; |clock_div|LessThan2~100 ; out0             ;
; |clock_div|LessThan2~101 ; |clock_div|LessThan2~101 ; out0             ;
; |clock_div|LessThan2~102 ; |clock_div|LessThan2~102 ; out0             ;
; |clock_div|LessThan2~103 ; |clock_div|LessThan2~103 ; out0             ;
; |clock_div|LessThan2~104 ; |clock_div|LessThan2~104 ; out0             ;
; |clock_div|LessThan2~105 ; |clock_div|LessThan2~105 ; out0             ;
; |clock_div|LessThan2~106 ; |clock_div|LessThan2~106 ; out0             ;
; |clock_div|LessThan2~107 ; |clock_div|LessThan2~107 ; out0             ;
; |clock_div|LessThan2~108 ; |clock_div|LessThan2~108 ; out0             ;
; |clock_div|LessThan2~109 ; |clock_div|LessThan2~109 ; out0             ;
; |clock_div|LessThan2~110 ; |clock_div|LessThan2~110 ; out0             ;
; |clock_div|LessThan2~111 ; |clock_div|LessThan2~111 ; out0             ;
; |clock_div|LessThan2~112 ; |clock_div|LessThan2~112 ; out0             ;
; |clock_div|LessThan2~113 ; |clock_div|LessThan2~113 ; out0             ;
; |clock_div|LessThan2~114 ; |clock_div|LessThan2~114 ; out0             ;
; |clock_div|Add0~100      ; |clock_div|Add0~100      ; out0             ;
; |clock_div|Add0~101      ; |clock_div|Add0~101      ; out0             ;
; |clock_div|Add0~102      ; |clock_div|Add0~102      ; out0             ;
; |clock_div|Add0~103      ; |clock_div|Add0~103      ; out0             ;
; |clock_div|Add0~104      ; |clock_div|Add0~104      ; out0             ;
+--------------------------+--------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------+
; Missing 1-Value Coverage                                             ;
+-------------------------+-------------------------+------------------+
; Node Name               ; Output Port Name        ; Output Port Type ;
+-------------------------+-------------------------+------------------+
; |clock_div|counter1~0   ; |clock_div|counter1~0   ; out              ;
; |clock_div|counter1~1   ; |clock_div|counter1~1   ; out              ;
; |clock_div|counter1~2   ; |clock_div|counter1~2   ; out              ;
; |clock_div|counter1~3   ; |clock_div|counter1~3   ; out              ;
; |clock_div|counter1~4   ; |clock_div|counter1~4   ; out              ;
; |clock_div|counter1~5   ; |clock_div|counter1~5   ; out              ;
; |clock_div|counter1~6   ; |clock_div|counter1~6   ; out              ;
; |clock_div|counter1~7   ; |clock_div|counter1~7   ; out              ;
; |clock_div|counter1~8   ; |clock_div|counter1~8   ; out              ;
; |clock_div|counter1~9   ; |clock_div|counter1~9   ; out              ;
; |clock_div|counter1~10  ; |clock_div|counter1~10  ; out              ;
; |clock_div|counter1~11  ; |clock_div|counter1~11  ; out              ;
; |clock_div|counter1~12  ; |clock_div|counter1~12  ; out              ;
; |clock_div|counter1~13  ; |clock_div|counter1~13  ; out              ;
; |clock_div|counter1~14  ; |clock_div|counter1~14  ; out              ;
; |clock_div|counter1~15  ; |clock_div|counter1~15  ; out              ;
; |clock_div|counter1~20  ; |clock_div|counter1~20  ; out              ;
; |clock_div|counter1~21  ; |clock_div|counter1~21  ; out              ;
; |clock_div|counter1~22  ; |clock_div|counter1~22  ; out              ;
; |clock_div|counter1~23  ; |clock_div|counter1~23  ; out              ;
; |clock_div|counter1~24  ; |clock_div|counter1~24  ; out              ;
; |clock_div|counter1~25  ; |clock_div|counter1~25  ; out              ;
; |clock_div|counter1~26  ; |clock_div|counter1~26  ; out              ;
; |clock_div|counter1~27  ; |clock_div|counter1~27  ; out              ;
; |clock_div|counter1~28  ; |clock_div|counter1~28  ; out              ;
; |clock_div|counter1~29  ; |clock_div|counter1~29  ; out              ;
; |clock_div|counter1~30  ; |clock_div|counter1~30  ; out              ;
; |clock_div|counter1~31  ; |clock_div|counter1~31  ; out              ;
; |clock_div|counter1~32  ; |clock_div|counter1~32  ; out              ;
; |clock_div|counter1~33  ; |clock_div|counter1~33  ; out              ;
; |clock_div|counter1~34  ; |clock_div|counter1~34  ; out              ;
; |clock_div|counter1~35  ; |clock_div|counter1~35  ; out              ;
; |clock_div|counter1~40  ; |clock_div|counter1~40  ; out              ;
; |clock_div|counter1~41  ; |clock_div|counter1~41  ; out              ;
; |clock_div|counter1~42  ; |clock_div|counter1~42  ; out              ;
; |clock_div|counter1~43  ; |clock_div|counter1~43  ; out              ;
; |clock_div|counter1~44  ; |clock_div|counter1~44  ; out              ;
; |clock_div|counter1~45  ; |clock_div|counter1~45  ; out              ;
; |clock_div|counter1~46  ; |clock_div|counter1~46  ; out              ;
; |clock_div|counter1~47  ; |clock_div|counter1~47  ; out              ;
; |clock_div|counter1~48  ; |clock_div|counter1~48  ; out              ;
; |clock_div|counter1~49  ; |clock_div|counter1~49  ; out              ;
; |clock_div|counter1~50  ; |clock_div|counter1~50  ; out              ;
; |clock_div|counter1~51  ; |clock_div|counter1~51  ; out              ;
; |clock_div|counter1~52  ; |clock_div|counter1~52  ; out              ;
; |clock_div|counter1~53  ; |clock_div|counter1~53  ; out              ;
; |clock_div|counter1~54  ; |clock_div|counter1~54  ; out              ;
; |clock_div|counter1~55  ; |clock_div|counter1~55  ; out              ;
; |clock_div|counter1[3]  ; |clock_div|counter1[3]  ; regout           ;
; |clock_div|counter1[4]  ; |clock_div|counter1[4]  ; regout           ;
; |clock_div|counter1[5]  ; |clock_div|counter1[5]  ; regout           ;
; |clock_div|counter1[6]  ; |clock_div|counter1[6]  ; regout           ;
; |clock_div|counter1[7]  ; |clock_div|counter1[7]  ; regout           ;
; |clock_div|counter1[8]  ; |clock_div|counter1[8]  ; regout           ;
; |clock_div|counter1[9]  ; |clock_div|counter1[9]  ; regout           ;
; |clock_div|counter1[10] ; |clock_div|counter1[10] ; regout           ;
; |clock_div|counter1[11] ; |clock_div|counter1[11] ; regout           ;
; |clock_div|counter1[12] ; |clock_div|counter1[12] ; regout           ;
; |clock_div|counter1[13] ; |clock_div|counter1[13] ; regout           ;
; |clock_div|counter1[14] ; |clock_div|counter1[14] ; regout           ;
; |clock_div|counter1[15] ; |clock_div|counter1[15] ; regout           ;
; |clock_div|counter1[16] ; |clock_div|counter1[16] ; regout           ;
; |clock_div|counter1[17] ; |clock_div|counter1[17] ; regout           ;
; |clock_div|counter1[18] ; |clock_div|counter1[18] ; regout           ;
; |clock_div|counter1[19] ; |clock_div|counter1[19] ; regout           ;
; |clock_div|Add0~105     ; |clock_div|Add0~105     ; out0             ;
; |clock_div|Add0~106     ; |clock_div|Add0~106     ; out0             ;
; |clock_div|Add0~107     ; |clock_div|Add0~107     ; out0             ;
; |clock_div|Add0~108     ; |clock_div|Add0~108     ; out0             ;
; |clock_div|Add0~109     ; |clock_div|Add0~109     ; out0             ;
; |clock_div|Add0~110     ; |clock_div|Add0~110     ; out0             ;
; |clock_div|Add0~111     ; |clock_div|Add0~111     ; out0             ;
; |clock_div|Add0~112     ; |clock_div|Add0~112     ; out0             ;
; |clock_div|Add0~113     ; |clock_div|Add0~113     ; out0             ;
; |clock_div|Add0~114     ; |clock_div|Add0~114     ; out0             ;
; |clock_div|Add0~115     ; |clock_div|Add0~115     ; out0             ;
; |clock_div|Add0~116     ; |clock_div|Add0~116     ; out0             ;