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📄 alt_u_div_cve.tdf

📁 基於DE2系統的LCM verilog code,在LCM右下方顯示數字,每按一次按鍵數字會加1,顏色也會改變
💻 TDF
字号:
--alt_u_div DEVICE_FAMILY="Cyclone II" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=2 WIDTH_N=4 WIDTH_Q=4 WIDTH_R=2 denominator numerator quotient remainder
--VERSION_BEGIN 7.1 cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION add_sub_lkc (dataa[0..0], datab[0..0])
RETURNS ( cout, result[0..0]);
FUNCTION add_sub_mkc (dataa[1..0], datab[1..0])
RETURNS ( cout, result[1..0]);

--synthesis_resources = lut 8 
SUBDESIGN alt_u_div_cve
( 
	den_out[1..0]	:	output;
	denominator[1..0]	:	input;
	numerator[3..0]	:	input;
	quotient[3..0]	:	output;
	remainder[1..0]	:	output;
) 
VARIABLE 
	add_sub_0 : add_sub_lkc;
	add_sub_1 : add_sub_mkc;
	add_sub_2_result_int[3..0]	:	WIRE;
	add_sub_2_cout	:	WIRE;
	add_sub_2_dataa[2..0]	:	WIRE;
	add_sub_2_datab[2..0]	:	WIRE;
	add_sub_2_result[2..0]	:	WIRE;
	add_sub_3_result_int[3..0]	:	WIRE;
	add_sub_3_cout	:	WIRE;
	add_sub_3_dataa[2..0]	:	WIRE;
	add_sub_3_datab[2..0]	:	WIRE;
	add_sub_3_result[2..0]	:	WIRE;
	DenominatorIn[14..0]	: WIRE;
	DenominatorIn_tmp[14..0]	: WIRE;
	gnd_wire	: WIRE;
	nose[19..0]	: WIRE;
	NumeratorIn[19..0]	: WIRE;
	NumeratorIn_tmp[19..0]	: WIRE;
	prestg[11..0]	: WIRE;
	quotient_tmp[3..0]	: WIRE;
	sel[9..0]	: WIRE;
	selnose[19..0]	: WIRE;
	StageIn[14..0]	: WIRE;
	StageIn_tmp[14..0]	: WIRE;
	StageOut[11..0]	: WIRE;

BEGIN 
	add_sub_0.dataa[0..0] = NumeratorIn[3..3];
	add_sub_0.datab[0..0] = DenominatorIn[0..0];
	add_sub_1.dataa[] = ( StageIn[3..3], NumeratorIn[6..6]);
	add_sub_1.datab[1..0] = DenominatorIn[4..3];
	add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
	add_sub_2_result[] = add_sub_2_result_int[2..0];
	add_sub_2_cout = !add_sub_2_result_int[3];
	add_sub_2_dataa[] = ( StageIn[7..6], NumeratorIn[9..9]);
	add_sub_2_datab[] = DenominatorIn[8..6];
	add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
	add_sub_3_result[] = add_sub_3_result_int[2..0];
	add_sub_3_cout = !add_sub_3_result_int[3];
	add_sub_3_dataa[] = ( StageIn[10..9], NumeratorIn[12..12]);
	add_sub_3_datab[] = DenominatorIn[11..9];
	den_out[1..0] = DenominatorIn[10..9];
	DenominatorIn[] = (gnd_wire # DenominatorIn_tmp[]);
	DenominatorIn_tmp[] = ( DenominatorIn[11..0], ( gnd_wire, denominator[]));
	gnd_wire = B"0";
	nose[] = ( B"0000", (add_sub_3_cout # gnd_wire), B"0000", (add_sub_2_cout # gnd_wire), B"0000", (add_sub_1.cout # gnd_wire), B"0000", (add_sub_0.cout # gnd_wire));
	NumeratorIn[] = (gnd_wire # NumeratorIn_tmp[]);
	NumeratorIn_tmp[] = ( NumeratorIn[15..0], numerator[]);
	prestg[] = ( add_sub_3_result[], add_sub_2_result[], GND, add_sub_1.result[], B"00", add_sub_0.result[]);
	quotient[] = quotient_tmp[];
	quotient_tmp[] = ( (! selnose[0..0]), (! selnose[5..5]), (! selnose[10..10]), (! selnose[15..15]));
	remainder[1..0] = StageIn[13..12];
	sel[] = ( gnd_wire, (gnd_wire # (sel[9..9] # DenominatorIn[13..13])), gnd_wire, (gnd_wire # (sel[7..7] # DenominatorIn[10..10])), gnd_wire, (gnd_wire # (sel[5..5] # DenominatorIn[7..7])), gnd_wire, (gnd_wire # (sel[3..3] # DenominatorIn[4..4])), gnd_wire, (gnd_wire # (sel[1..1] # DenominatorIn[1..1])));
	selnose[] = ( (gnd_wire # (! nose[19..19])), (gnd_wire # (! nose[18..18])), ((gnd_wire # (! nose[17..17])) # sel[9..9]), ((gnd_wire # (! nose[16..16])) # sel[8..8]), (gnd_wire # (! nose[15..15])), (gnd_wire # (! nose[14..14])), ((gnd_wire # (! nose[13..13])) # sel[7..7]), ((gnd_wire # (! nose[12..12])) # sel[6..6]), (gnd_wire # (! nose[11..11])), (gnd_wire # (! nose[10..10])), ((gnd_wire # (! nose[9..9])) # sel[5..5]), ((gnd_wire # (! nose[8..8])) # sel[4..4]), (gnd_wire # (! nose[7..7])), (gnd_wire # (! nose[6..6])), ((gnd_wire # (! nose[5..5])) # sel[3..3]), ((gnd_wire # (! nose[4..4])) # sel[2..2]), (gnd_wire # (! nose[3..3])), (gnd_wire # (! nose[2..2])), ((gnd_wire # (! nose[1..1])) # sel[1..1]), ((gnd_wire # (! nose[0..0])) # sel[0..0]));
	StageIn[] = (gnd_wire # StageIn_tmp[]);
	StageIn_tmp[] = ( StageOut[11..0], B"000");
	StageOut[] = ( ((( StageIn[10..9], NumeratorIn[12..12]) & selnose[15..15]) # (prestg[11..9] & (! selnose[15..15]))), ((( StageIn[7..6], NumeratorIn[9..9]) & selnose[10..10]) # (prestg[8..6] & (! selnose[10..10]))), ((( StageIn[4..3], NumeratorIn[6..6]) & selnose[5..5]) # (prestg[5..3] & (! selnose[5..5]))), ((( StageIn[1..0], NumeratorIn[3..3]) & selnose[0..0]) # (prestg[2..0] & (! selnose[0..0]))));
END;
--VALID FILE

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