de2_lcm_test.tan.rpt

基於DE2系統的LCM verilog code,在LCM右下方顯示數字,每按一次按鍵數字會加1,顏色也會改變

; Clock Hold: 'CLOCK_50'                                  ; 0.391 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                                            ; I2S_LCM_Config:u4|LUT_INDEX[0] ; I2S_LCM_Config:u4|LUT_INDEX[0]                ; CLOCK_50                                 ; CLOCK_50                                 ; 0            ;
; Total number of failed paths                            ;           ;                                  ;                                                ;                                ;                                               ;                                          ;                                          ; 0            ;
+---------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+--------------------------------+-----------------------------------------------+------------------------------------------+------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                           ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                          ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; LCM_PLL:u0|altpll:altpll_component|_clk0 ;                    ; PLL output ; 18.42 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 7                     ; 19                  ; -2.358 ns ;              ;
; CLOCK_50                                 ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; KEY[1]                                   ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'LCM_PLL:u0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From       ; To          ; From Clock                               ; To Clock                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 49.825 ns                               ; 224.22 MHz ( period = 4.460 ns )                    ; H_Cont[5]  ; V_Cont[0]   ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.075 ns                 ; 4.250 ns                ;
; 49.825 ns                               ; 224.22 MHz ( period = 4.460 ns )                    ; H_Cont[5]  ; V_Cont[3]   ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.075 ns                 ; 4.250 ns                ;
; 49.825 ns                               ; 224.22 MHz ( period = 4.460 ns )                    ; H_Cont[5]  ; V_Cont[5]   ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.075 ns                 ; 4.250 ns                ;
; 49.825 ns                               ; 224.22 MHz ( period = 4.460 ns )                    ; H_Cont[5]  ; V_Cont[6]   ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.075 ns                 ; 4.250 ns                ;
; 49.825 ns                               ; 224.22 MHz ( period = 4.460 ns )                    ; H_Cont[5]  ; V_Cont[4]   ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.075 ns                 ; 4.250 ns                ;
; 49.825 ns                               ; 224.22 MHz ( period = 4.460 ns )                    ; H_Cont[5]  ; V_Cont[2]   ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.075 ns                 ; 4.250 ns                ;
; 49.825 ns                               ; 224.22 MHz ( period = 4.460 ns )                    ; H_Cont[5]  ; V_Cont[1]   ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.075 ns                 ; 4.250 ns                ;
; 49.825 ns                               ; 224.22 MHz ( period = 4.460 ns )                    ; H_Cont[5]  ; V_Cont[7]   ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.075 ns                 ; 4.250 ns                ;
; 49.825 ns                               ; 224.22 MHz ( period = 4.460 ns )                    ; H_Cont[5]  ; V_Cont[9]   ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.075 ns                 ; 4.250 ns                ;
; 49.825 ns                               ; 224.22 MHz ( period = 4.460 ns )                    ; H_Cont[5]  ; V_Cont[10]  ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.075 ns                 ; 4.250 ns                ;
; 49.825 ns                               ; 224.22 MHz ( period = 4.460 ns )                    ; H_Cont[5]  ; V_Cont[8]   ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; LCM_PLL:u0|altpll:altpll_component|_clk0 ; 54.285 ns                   ; 54.075 ns                 ; 4.250 ns                ;