light.tan.summary

自己写的一个VHDL程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -2.400 ns
From           : Hold
To             : controller:inst|numa[2]
From Clock     : --
To Clock       : Clk25MHz
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.500 ns
From           : controller:inst|reda
To             : RedA
From Clock     : Clk25MHz
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 9.000 ns
From           : Hold
To             : controller:inst|numa[2]
From Clock     : --
To Clock       : Clk25MHz
Failed Paths   : 0

Type           : Clock Setup: 'Clk25MHz'
Slack          : N/A
Required Time  : None
Actual Time    : 23.81 MHz ( period = 42.000 ns )
From           : controller:inst|numa[2]
To             : display:inst5|display[2]
From Clock     : Clk25MHz
To Clock       : Clk25MHz
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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