light.tan.qmsg

自己写的一个VHDL程序

{ "Info" "ITDB_FULL_TCO_RESULT" "Clk25MHz YellowA controller:inst\|yellowa 14.500 ns register " "Info: tco from clock \"Clk25MHz\" to destination pin \"YellowA\" through register \"controller:inst\|yellowa\" is 14.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk25MHz source 11.500 ns + Longest register " "Info: + Longest clock path from clock \"Clk25MHz\" to source register is 11.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk25MHz 1 CLK PIN_83 22 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'Clk25MHz'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk25MHz } "NODE_NAME" } } { "light.bdf" "" { Schematic "E:/practice/Quartus/light/light.bdf" { { -72 64 232 -56 "Clk25MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.500 ns predevide2:inst9\|Clk 2 REG LC6 27 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.500 ns; Loc. = LC6; Fanout = 27; REG Node = 'predevide2:inst9\|Clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { Clk25MHz predevide2:inst9|Clk } "NODE_NAME" } } { "predevide2.vhd" "" { Text "E:/practice/Quartus/light/predevide2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.000 ns) 7.500 ns FreDevide10:inst8\|Clk 3 REG LC70 16 " "Info: 3: + IC(1.000 ns) + CELL(4.000 ns) = 7.500 ns; Loc. = LC70; Fanout = 16; REG Node = 'FreDevide10:inst8\|Clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { predevide2:inst9|Clk FreDevide10:inst8|Clk } "NODE_NAME" } } { "FreDevide10.vhd" "" { Text "E:/practice/Quartus/light/FreDevide10.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 11.500 ns controller:inst\|yellowa 4 REG LC57 1 " "Info: 4: + IC(1.000 ns) + CELL(3.000 ns) = 11.500 ns; Loc. = LC57; Fanout = 1; REG Node = 'controller:inst\|yellowa'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { FreDevide10:inst8|Clk controller:inst|yellowa } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.500 ns ( 82.61 % ) " "Info: Total cell delay = 9.500 ns ( 82.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 17.39 % ) " "Info: Total interconnect delay = 2.000 ns ( 17.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { Clk25MHz predevide2:inst9|Clk FreDevide10:inst8|Clk controller:inst|yellowa } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { Clk25MHz {} Clk25MHz~out {} predevide2:inst9|Clk {} FreDevide10:inst8|Clk {} controller:inst|yellowa {} } { 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 1.000ns 4.000ns 3.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.000 ns + Longest register pin " "Info: + Longest register to pin delay is 2.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns controller:inst\|yellowa 1 REG LC57 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC57; Fanout = 1; REG Node = 'controller:inst\|yellowa'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { controller:inst|yellowa } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns YellowA 2 PIN PIN_36 0 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'YellowA'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { controller:inst|yellowa YellowA } "NODE_NAME" } } { "light.bdf" "" { Schematic "E:/practice/Quartus/light/light.bdf" { { 112 680 856 128 "YellowA" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 100.00 % ) " "Info: Total cell delay = 2.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { controller:inst|yellowa YellowA } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.000 ns" { controller:inst|yellowa {} YellowA {} } { 0.000ns 0.000ns } { 0.000ns 2.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { Clk25MHz predevide2:inst9|Clk FreDevide10:inst8|Clk controller:inst|yellowa } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { Clk25MHz {} Clk25MHz~out {} predevide2:inst9|Clk {} FreDevide10:inst8|Clk {} controller:inst|yellowa {} } { 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 1.000ns 4.000ns 3.000ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { controller:inst|yellowa YellowA } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.000 ns" { controller:inst|yellowa {} YellowA {} } { 0.000ns 0.000ns } { 0.000ns 2.000ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "controller:inst\|flash Hold Clk25MHz 9.000 ns register " "Info: th for register \"controller:inst\|flash\" (data pin = \"Hold\", clock pin = \"Clk25MHz\") is 9.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk25MHz destination 11.500 ns + Longest register " "Info: + Longest clock path from clock \"Clk25MHz\" to destination register is 11.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk25MHz 1 CLK PIN_83 22 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'Clk25MHz'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk25MHz } "NODE_NAME" } } { "light.bdf" "" { Schematic "E:/practice/Quartus/light/light.bdf" { { -72 64 232 -56 "Clk25MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.500 ns predevide2:inst9\|Clk 2 REG LC6 27 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.500 ns; Loc. = LC6; Fanout = 27; REG Node = 'predevide2:inst9\|Clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { Clk25MHz predevide2:inst9|Clk } "NODE_NAME" } } { "predevide2.vhd" "" { Text "E:/practice/Quartus/light/predevide2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.000 ns) 7.500 ns FreDevide10:inst8\|Clk 3 REG LC70 16 " "Info: 3: + IC(1.000 ns) + CELL(4.000 ns) = 7.500 ns; Loc. = LC70; Fanout = 16; REG Node = 'FreDevide10:inst8\|Clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { predevide2:inst9|Clk FreDevide10:inst8|Clk } "NODE_NAME" } } { "FreDevide10.vhd" "" { Text "E:/practice/Quartus/light/FreDevide10.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 11.500 ns controller:inst\|flash 4 REG LC59 21 " "Info: 4: + IC(1.000 ns) + CELL(3.000 ns) = 11.500 ns; Loc. = LC59; Fanout = 21; REG Node = 'controller:inst\|flash'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { FreDevide10:inst8|Clk controller:inst|flash } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.500 ns ( 82.61 % ) " "Info: Total cell delay = 9.500 ns ( 82.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 17.39 % ) " "Info: Total interconnect delay = 2.000 ns ( 17.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { Clk25MHz predevide2:inst9|Clk FreDevide10:inst8|Clk controller:inst|flash } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { Clk25MHz {} Clk25MHz~out {} predevide2:inst9|Clk {} FreDevide10:inst8|Clk {} controller:inst|flash {} } { 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 1.000ns 4.000ns 3.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "2.000 ns + " "Info: + Micro hold delay of destination is 2.000 ns" {  } { { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns Hold 1 PIN PIN_6 63 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_6; Fanout = 63; PIN Node = 'Hold'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { Hold } "NODE_NAME" } } { "light.bdf" "" { Schematic "E:/practice/Quartus/light/light.bdf" { { 112 64 232 128 "Hold" "" } { 56 448 486 72 "Hold" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 4.500 ns controller:inst\|flash 2 REG LC59 21 " "Info: 2: + IC(1.000 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC59; Fanout = 21; REG Node = 'controller:inst\|flash'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { Hold controller:inst|flash } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 77.78 % ) " "Info: Total cell delay = 3.500 ns ( 77.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 22.22 % ) " "Info: Total interconnect delay = 1.000 ns ( 22.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { Hold controller:inst|flash } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "4.500 ns" { Hold {} Hold~out {} controller:inst|flash {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 3.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { Clk25MHz predevide2:inst9|Clk FreDevide10:inst8|Clk controller:inst|flash } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { Clk25MHz {} Clk25MHz~out {} predevide2:inst9|Clk {} FreDevide10:inst8|Clk {} controller:inst|flash {} } { 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 1.000ns 4.000ns 3.000ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { Hold controller:inst|flash } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "4.500 ns" { Hold {} Hold~out {} controller:inst|flash {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 3.000ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 05 08:23:16 2008 " "Info: Processing ended: Mon May 05 08:23:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}