light.tan.qmsg

自己写的一个VHDL程序

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk25MHz " "Info: Assuming node \"Clk25MHz\" is an undefined clock" {  } { { "light.bdf" "" { Schematic "E:/practice/Quartus/light/light.bdf" { { -72 64 232 -56 "Clk25MHz" "" } } } } { "d:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clk25MHz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "FreDevide10:inst8\|Clk " "Info: Detected ripple clock \"FreDevide10:inst8\|Clk\" as buffer" {  } { { "FreDevide10.vhd" "" { Text "E:/practice/Quartus/light/FreDevide10.vhd" 19 -1 0 } } { "d:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "FreDevide10:inst8\|Clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "predevide2:inst9\|Clk " "Info: Detected ripple clock \"predevide2:inst9\|Clk\" as buffer" {  } { { "predevide2.vhd" "" { Text "E:/practice/Quartus/light/predevide2.vhd" 19 -1 0 } } { "d:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "predevide2:inst9\|Clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk25MHz register controller:inst\|numa\[0\] register display:inst5\|display\[2\] 23.81 MHz 42.0 ns Internal " "Info: Clock \"Clk25MHz\" has Internal fmax of 23.81 MHz between source register \"controller:inst\|numa\[0\]\" and destination register \"display:inst5\|display\[2\]\" (period= 42.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.000 ns + Longest register register " "Info: + Longest register to register delay is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns controller:inst\|numa\[0\] 1 REG LC52 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC52; Fanout = 23; REG Node = 'controller:inst\|numa\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { controller:inst|numa[0] } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.000 ns) 5.000 ns display:inst5\|Mux1~498 2 COMB SEXP25 1 " "Info: 2: + IC(1.000 ns) + CELL(4.000 ns) = 5.000 ns; Loc. = SEXP25; Fanout = 1; COMB Node = 'display:inst5\|Mux1~498'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { controller:inst|numa[0] display:inst5|Mux1~498 } "NODE_NAME" } } { "display.vhd" "" { Text "E:/practice/Quartus/light/display.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 9.000 ns display:inst5\|Mux1~505sexpand3 3 COMB SEXP30 1 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 9.000 ns; Loc. = SEXP30; Fanout = 1; COMB Node = 'display:inst5\|Mux1~505sexpand3'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { display:inst5|Mux1~498 display:inst5|Mux1~505sexpand3 } "NODE_NAME" } } { "display.vhd" "" { Text "E:/practice/Quartus/light/display.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 12.000 ns display:inst5\|display\[2\] 4 REG LC25 1 " "Info: 4: + IC(0.000 ns) + CELL(3.000 ns) = 12.000 ns; Loc. = LC25; Fanout = 1; REG Node = 'display:inst5\|display\[2\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { display:inst5|Mux1~505sexpand3 display:inst5|display[2] } "NODE_NAME" } } { "display.vhd" "" { Text "E:/practice/Quartus/light/display.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns ( 91.67 % ) " "Info: Total cell delay = 11.000 ns ( 91.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 8.33 % ) " "Info: Total interconnect delay = 1.000 ns ( 8.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { controller:inst|numa[0] display:inst5|Mux1~498 display:inst5|Mux1~505sexpand3 display:inst5|display[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { controller:inst|numa[0] {} display:inst5|Mux1~498 {} display:inst5|Mux1~505sexpand3 {} display:inst5|display[2] {} } { 0.000ns 1.000ns 0.000ns 0.000ns } { 0.000ns 4.000ns 4.000ns 3.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.000 ns - Smallest " "Info: - Smallest clock skew is -5.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk25MHz destination 6.500 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk25MHz\" to destination register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk25MHz 1 CLK PIN_83 22 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'Clk25MHz'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk25MHz } "NODE_NAME" } } { "light.bdf" "" { Schematic "E:/practice/Quartus/light/light.bdf" { { -72 64 232 -56 "Clk25MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.500 ns predevide2:inst9\|Clk 2 REG LC6 27 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.500 ns; Loc. = LC6; Fanout = 27; REG Node = 'predevide2:inst9\|Clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { Clk25MHz predevide2:inst9|Clk } "NODE_NAME" } } { "predevide2.vhd" "" { Text "E:/practice/Quartus/light/predevide2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 6.500 ns display:inst5\|display\[2\] 3 REG LC25 1 " "Info: 3: + IC(1.000 ns) + CELL(3.000 ns) = 6.500 ns; Loc. = LC25; Fanout = 1; REG Node = 'display:inst5\|display\[2\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { predevide2:inst9|Clk display:inst5|display[2] } "NODE_NAME" } } { "display.vhd" "" { Text "E:/practice/Quartus/light/display.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { Clk25MHz predevide2:inst9|Clk display:inst5|display[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { Clk25MHz {} Clk25MHz~out {} predevide2:inst9|Clk {} display:inst5|display[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 1.000ns 3.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk25MHz source 11.500 ns - Longest register " "Info: - Longest clock path from clock \"Clk25MHz\" to source register is 11.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk25MHz 1 CLK PIN_83 22 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'Clk25MHz'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk25MHz } "NODE_NAME" } } { "light.bdf" "" { Schematic "E:/practice/Quartus/light/light.bdf" { { -72 64 232 -56 "Clk25MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.500 ns predevide2:inst9\|Clk 2 REG LC6 27 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.500 ns; Loc. = LC6; Fanout = 27; REG Node = 'predevide2:inst9\|Clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { Clk25MHz predevide2:inst9|Clk } "NODE_NAME" } } { "predevide2.vhd" "" { Text "E:/practice/Quartus/light/predevide2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.000 ns) 7.500 ns FreDevide10:inst8\|Clk 3 REG LC70 16 " "Info: 3: + IC(1.000 ns) + CELL(4.000 ns) = 7.500 ns; Loc. = LC70; Fanout = 16; REG Node = 'FreDevide10:inst8\|Clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { predevide2:inst9|Clk FreDevide10:inst8|Clk } "NODE_NAME" } } { "FreDevide10.vhd" "" { Text "E:/practice/Quartus/light/FreDevide10.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 11.500 ns controller:inst\|numa\[0\] 4 REG LC52 23 " "Info: 4: + IC(1.000 ns) + CELL(3.000 ns) = 11.500 ns; Loc. = LC52; Fanout = 23; REG Node = 'controller:inst\|numa\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { FreDevide10:inst8|Clk controller:inst|numa[0] } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.500 ns ( 82.61 % ) " "Info: Total cell delay = 9.500 ns ( 82.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 17.39 % ) " "Info: Total interconnect delay = 2.000 ns ( 17.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { Clk25MHz predevide2:inst9|Clk FreDevide10:inst8|Clk controller:inst|numa[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { Clk25MHz {} Clk25MHz~out {} predevide2:inst9|Clk {} FreDevide10:inst8|Clk {} controller:inst|numa[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 1.000ns 4.000ns 3.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { Clk25MHz predevide2:inst9|Clk display:inst5|display[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { Clk25MHz {} Clk25MHz~out {} predevide2:inst9|Clk {} display:inst5|display[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 1.000ns 3.000ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { Clk25MHz predevide2:inst9|Clk FreDevide10:inst8|Clk controller:inst|numa[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { Clk25MHz {} Clk25MHz~out {} predevide2:inst9|Clk {} FreDevide10:inst8|Clk {} controller:inst|numa[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 1.000ns 4.000ns 3.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.000 ns + " "Info: + Micro setup delay of destination is 3.000 ns" {  } { { "display.vhd" "" { Text "E:/practice/Quartus/light/display.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 18 -1 0 } } { "display.vhd" "" { Text "E:/practice/Quartus/light/display.vhd" 18 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { controller:inst|numa[0] display:inst5|Mux1~498 display:inst5|Mux1~505sexpand3 display:inst5|display[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { controller:inst|numa[0] {} display:inst5|Mux1~498 {} display:inst5|Mux1~505sexpand3 {} display:inst5|display[2] {} } { 0.000ns 1.000ns 0.000ns 0.000ns } { 0.000ns 4.000ns 4.000ns 3.000ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { Clk25MHz predevide2:inst9|Clk display:inst5|display[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { Clk25MHz {} Clk25MHz~out {} predevide2:inst9|Clk {} display:inst5|display[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 1.000ns 3.000ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { Clk25MHz predevide2:inst9|Clk FreDevide10:inst8|Clk controller:inst|numa[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { Clk25MHz {} Clk25MHz~out {} predevide2:inst9|Clk {} FreDevide10:inst8|Clk {} controller:inst|numa[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 1.000ns 4.000ns 3.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "controller:inst\|numa\[3\] Hold Clk25MHz -2.400 ns register " "Info: tsu for register \"controller:inst\|numa\[3\]\" (data pin = \"Hold\", clock pin = \"Clk25MHz\") is -2.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Longest pin register " "Info: + Longest pin to register delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns Hold 1 PIN PIN_6 63 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_6; Fanout = 63; PIN Node = 'Hold'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { Hold } "NODE_NAME" } } { "light.bdf" "" { Schematic "E:/practice/Quartus/light/light.bdf" { { 112 64 232 128 "Hold" "" } { 56 448 486 72 "Hold" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 4.500 ns controller:inst\|numa\[3\]~1716 2 COMB LC81 1 " "Info: 2: + IC(1.000 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC81; Fanout = 1; COMB Node = 'controller:inst\|numa\[3\]~1716'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { Hold controller:inst|numa[3]~1716 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 5.300 ns controller:inst\|numa\[3\]~1719 3 COMB LC82 1 " "Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 5.300 ns; Loc. = LC82; Fanout = 1; COMB Node = 'controller:inst\|numa\[3\]~1719'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { controller:inst|numa[3]~1716 controller:inst|numa[3]~1719 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 6.100 ns controller:inst\|numa\[3\] 4 REG LC83 40 " "Info: 4: + IC(0.000 ns) + CELL(0.800 ns) = 6.100 ns; Loc. = LC83; Fanout = 40; REG Node = 'controller:inst\|numa\[3\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { controller:inst|numa[3]~1719 controller:inst|numa[3] } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 83.61 % ) " "Info: Total cell delay = 5.100 ns ( 83.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.39 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { Hold controller:inst|numa[3]~1716 controller:inst|numa[3]~1719 controller:inst|numa[3] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { Hold {} Hold~out {} controller:inst|numa[3]~1716 {} controller:inst|numa[3]~1719 {} controller:inst|numa[3] {} } { 0.000ns 0.000ns 1.000ns 0.000ns 0.000ns } { 0.000ns 0.500ns 3.000ns 0.800ns 0.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.000 ns + " "Info: + Micro setup delay of destination is 3.000 ns" {  } { { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk25MHz destination 11.500 ns - Shortest register " "Info: - Shortest clock path from clock \"Clk25MHz\" to destination register is 11.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk25MHz 1 CLK PIN_83 22 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'Clk25MHz'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk25MHz } "NODE_NAME" } } { "light.bdf" "" { Schematic "E:/practice/Quartus/light/light.bdf" { { -72 64 232 -56 "Clk25MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.500 ns predevide2:inst9\|Clk 2 REG LC6 27 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.500 ns; Loc. = LC6; Fanout = 27; REG Node = 'predevide2:inst9\|Clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { Clk25MHz predevide2:inst9|Clk } "NODE_NAME" } } { "predevide2.vhd" "" { Text "E:/practice/Quartus/light/predevide2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.000 ns) 7.500 ns FreDevide10:inst8\|Clk 3 REG LC70 16 " "Info: 3: + IC(1.000 ns) + CELL(4.000 ns) = 7.500 ns; Loc. = LC70; Fanout = 16; REG Node = 'FreDevide10:inst8\|Clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { predevide2:inst9|Clk FreDevide10:inst8|Clk } "NODE_NAME" } } { "FreDevide10.vhd" "" { Text "E:/practice/Quartus/light/FreDevide10.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 11.500 ns controller:inst\|numa\[3\] 4 REG LC83 40 " "Info: 4: + IC(1.000 ns) + CELL(3.000 ns) = 11.500 ns; Loc. = LC83; Fanout = 40; REG Node = 'controller:inst\|numa\[3\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { FreDevide10:inst8|Clk controller:inst|numa[3] } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/practice/Quartus/light/controller.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.500 ns ( 82.61 % ) " "Info: Total cell delay = 9.500 ns ( 82.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 17.39 % ) " "Info: Total interconnect delay = 2.000 ns ( 17.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { Clk25MHz predevide2:inst9|Clk FreDevide10:inst8|Clk controller:inst|numa[3] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { Clk25MHz {} Clk25MHz~out {} predevide2:inst9|Clk {} FreDevide10:inst8|Clk {} controller:inst|numa[3] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 1.000ns 4.000ns 3.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { Hold controller:inst|numa[3]~1716 controller:inst|numa[3]~1719 controller:inst|numa[3] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { Hold {} Hold~out {} controller:inst|numa[3]~1716 {} controller:inst|numa[3]~1719 {} controller:inst|numa[3] {} } { 0.000ns 0.000ns 1.000ns 0.000ns 0.000ns } { 0.000ns 0.500ns 3.000ns 0.800ns 0.800ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { Clk25MHz predevide2:inst9|Clk FreDevide10:inst8|Clk controller:inst|numa[3] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { Clk25MHz {} Clk25MHz~out {} predevide2:inst9|Clk {} FreDevide10:inst8|Clk {} controller:inst|numa[3] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 1.000ns 4.000ns 3.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}