counter.vhd

自己写的一个VHDL程序

library ieee;
use ieee.std_logic_1164.all;

entity counter is
port
(clock:in std_logic;
 reset:in std_logic;
  hold:in std_logic;
 counternum: buffer integer range 0 to 49
);
end;

architecture behavior of counter is
  begin
  process(reset,clock)
  begin
    if reset='1' then
       counternum<=0;
    elsif rising_edge(clock) then
       if hold='1' then
          counternum<=counternum;
       else
         if counternum=49 then
            counternum<=0;
         else
            counternum<=counternum+1;
         end if;
       end if;
     end if;
  end process;
end;