fenwei.vhd

自己写的一个VHDL程序

library ieee;
use ieee.std_logic_1164.all;

entity fenwei is
port
(numin:in integer range 0 to 25;
 numa,numb:out integer range 0 to 9);
end;

architecture behavior of fenwei is
begin
  process(numin)
  begin
   if numin>=20 then
      numa<=2;
      numb<=numin-20;
   elsif numin>=10 then
      numa<=1;
      numb<=numin-10;
   else
      numa<=0;
      numb<=numin;
   end if;
  end process;
end;