up3_clock.map.rpt

来自「采用vhdl语言编写的UP3开发板电子钟程序。在quartus中编译完成。」· RPT 代码 · 共 263 行 · 第 1/5 页

; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                               ; Unlimited          ; Unlimited          ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Maximum Number of M-RAM Memory Blocks                              ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; UP3_CLOCK.vhd                    ; yes             ; User VHDL File  ; D:/EDA/Ex5/UP3_CLOCK.vhd     ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 683   ;
;     -- Combinational with no register       ; 332   ;
;     -- Register only                        ; 55    ;
;     -- Combinational with a register        ; 296   ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 303   ;
;     -- 3 input functions                    ; 132   ;
;     -- 2 input functions                    ; 173   ;
;     -- 1 input functions                    ; 18    ;
;     -- 0 input functions                    ; 2     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 600   ;
;     -- arithmetic mode                      ; 83    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 80    ;
;     -- asynchronous clear/load mode         ; 294   ;
;                                             ;       ;
; Total registers                             ; 351   ;
; Total logic cells in carry chains           ; 88    ;
; I/O pins                                    ; 24    ;