up3_clock.tan.summary

采用vhdl语言编写的UP3开发板电子钟程序。在quartus中编译完成。

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 9.241 ns
From           : reset
To             : set_yrd3[2]
From Clock     : --
To Clock       : clk_48Mhz
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.411 ns
From           : alarm_led~reg0
To             : alarm_led
From Clock     : clk_48Mhz
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.419 ns
From           : alarm
To             : current.alarm_on
From Clock     : --
To Clock       : clk_48Mhz
Failed Paths   : 0

Type           : Clock Setup: 'clk_48Mhz'
Slack          : N/A
Required Time  : None
Actual Time    : 110.42 MHz ( period = 9.056 ns )
From           : bcd_yrd2[2]
To             : DATA_BUS_VALUE[2]
From Clock     : clk_48Mhz
To Clock       : clk_48Mhz
Failed Paths   : 0

Type           : Clock Hold: 'clk_48Mhz'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : alarm_SECD1[0]
To             : current.alarm_on
From Clock     : clk_48Mhz
To Clock       : clk_48Mhz
Failed Paths   : 134

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 134

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