enc_bb.v

来自「Altera IP应用设计实例 &#61548 “Example-b4-2P」· Verilog 代码 · 共 54 行

// Generated by ed8b10b 1.4.0 [Altera, IP Toolbench v1.2.3 build12]
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// Copyright (C) 1991-2004 Altera Corporation
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// support information, device programming or simulation file, and any other
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// under Altera's Megafunction Partnership Program may be used only to
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module ENC (
	clk,
	reset_n,
	idle_ins,
	kin,
	ena,
	datain,
	rdin,
	rdforce,
	kerr,
	dataout,
	valid,
	rdout,
	rdcascade);

	input		clk;
	input		reset_n;
	input		idle_ins;
	input		kin;
	input		ena;
	input	[7:0]	datain;
	input		rdin;
	input		rdforce;
	output		kerr;
	output	[9:0]	dataout;
	output		valid;
	output		rdout;
	output		rdcascade;
endmodule