sine64.tan.qmsg

chdl 64位计数器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|ram_block1a7~porta_address_reg0 memory rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|q_a\[7\] 197.01 MHz 5.076 ns Internal " "Info: Clock \"clk\" has Internal fmax of 197.01 MHz between source memory \"rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|ram_block1a7~porta_address_reg0\" and destination memory \"rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|q_a\[7\]\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|ram_block1a7~porta_address_reg0 1 MEM M4K_X13_Y1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|ram_block1a7~porta_address_reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_8v21.tdf" "" { Text "D:/zyp/sine/db/altsyncram_8v21.tdf" 183 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|q_a\[7\] 2 MEM M4K_X13_Y1 1 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|q_a\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] } "NODE_NAME" } } { "db/altsyncram_8v21.tdf" "" { Text "D:/zyp/sine/db/altsyncram_8v21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.740 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sine64.bdf" "" { Schematic "D:/zyp/sine/sine64.bdf" { { 168 88 256 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.708 ns) 2.740 ns rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|q_a\[7\] 2 MEM M4K_X13_Y1 1 " "Info: 2: + IC(0.563 ns) + CELL(0.708 ns) = 2.740 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|q_a\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.271 ns" { clk rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] } "NODE_NAME" } } { "db/altsyncram_8v21.tdf" "" { Text "D:/zyp/sine/db/altsyncram_8v21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 79.45 % ) " "Info: Total cell delay = 2.177 ns ( 79.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.55 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.754 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sine64.bdf" "" { Schematic "D:/zyp/sine/sine64.bdf" { { 168 88 256 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.722 ns) 2.754 ns rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|ram_block1a7~porta_address_reg0 2 MEM M4K_X13_Y1 8 " "Info: 2: + IC(0.563 ns) + CELL(0.722 ns) = 2.754 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|ram_block1a7~porta_address_reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.285 ns" { clk rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_8v21.tdf" "" { Text "D:/zyp/sine/db/altsyncram_8v21.tdf" 183 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 79.56 % ) " "Info: Total cell delay = 2.191 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.754 ns" { clk rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.754 ns" { clk clk~out0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.708ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.754 ns" { clk rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.754 ns" { clk clk~out0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_8v21.tdf" "" { Text "D:/zyp/sine/db/altsyncram_8v21.tdf" 183 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_8v21.tdf" "" { Text "D:/zyp/sine/db/altsyncram_8v21.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.708ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.754 ns" { clk rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.754 ns" { clk clk~out0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[5\] rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|q_a\[5\] 7.764 ns memory " "Info: tco from clock \"clk\" to destination pin \"q\[5\]\" through memory \"rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|q_a\[5\]\" is 7.764 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.740 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sine64.bdf" "" { Schematic "D:/zyp/sine/sine64.bdf" { { 168 88 256 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.708 ns) 2.740 ns rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|q_a\[5\] 2 MEM M4K_X13_Y1 1 " "Info: 2: + IC(0.563 ns) + CELL(0.708 ns) = 2.740 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|q_a\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.271 ns" { clk rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] } "NODE_NAME" } } { "db/altsyncram_8v21.tdf" "" { Text "D:/zyp/sine/db/altsyncram_8v21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 79.45 % ) " "Info: Total cell delay = 2.177 ns ( 79.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.55 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_8v21.tdf" "" { Text "D:/zyp/sine/db/altsyncram_8v21.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.374 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.374 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|q_a\[5\] 1 MEM M4K_X13_Y1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'rom64:inst1\|altsyncram:altsyncram_component\|altsyncram_8v21:auto_generated\|q_a\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] } "NODE_NAME" } } { "db/altsyncram_8v21.tdf" "" { Text "D:/zyp/sine/db/altsyncram_8v21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.162 ns) + CELL(2.108 ns) 4.374 ns q\[5\] 2 PIN PIN_70 0 " "Info: 2: + IC(2.162 ns) + CELL(2.108 ns) = 4.374 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'q\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.270 ns" { rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] q[5] } "NODE_NAME" } } { "sine64.bdf" "" { Schematic "D:/zyp/sine/sine64.bdf" { { 176 752 928 192 "q\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.212 ns ( 50.57 % ) " "Info: Total cell delay = 2.212 ns ( 50.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.162 ns ( 49.43 % ) " "Info: Total interconnect delay = 2.162 ns ( 49.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.374 ns" { rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] q[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.374 ns" { rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] q[5] } { 0.000ns 2.162ns } { 0.104ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.708ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.374 ns" { rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] q[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.374 ns" { rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] q[5] } { 0.000ns 2.162ns } { 0.104ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 24 15:25:35 2007 " "Info: Processing ended: Sat Mar 24 15:25:35 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}