sine64.hier_info

chdl 64位计数器

|sine64
q[0] <= rom64:inst1.q[0]
q[1] <= rom64:inst1.q[1]
q[2] <= rom64:inst1.q[2]
q[3] <= rom64:inst1.q[3]
q[4] <= rom64:inst1.q[4]
q[5] <= rom64:inst1.q[5]
q[6] <= rom64:inst1.q[6]
q[7] <= rom64:inst1.q[7]
clk => rom64:inst1.clock
clk => cnt64:inst.clk


|sine64|rom64:inst1
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|sine64|rom64:inst1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_8v21:auto_generated.address_a[0]
address_a[1] => altsyncram_8v21:auto_generated.address_a[1]
address_a[2] => altsyncram_8v21:auto_generated.address_a[2]
address_a[3] => altsyncram_8v21:auto_generated.address_a[3]
address_a[4] => altsyncram_8v21:auto_generated.address_a[4]
address_a[5] => altsyncram_8v21:auto_generated.address_a[5]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_8v21:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_8v21:auto_generated.q_a[0]
q_a[1] <= altsyncram_8v21:auto_generated.q_a[1]
q_a[2] <= altsyncram_8v21:auto_generated.q_a[2]
q_a[3] <= altsyncram_8v21:auto_generated.q_a[3]
q_a[4] <= altsyncram_8v21:auto_generated.q_a[4]
q_a[5] <= altsyncram_8v21:auto_generated.q_a[5]
q_a[6] <= altsyncram_8v21:auto_generated.q_a[6]
q_a[7] <= altsyncram_8v21:auto_generated.q_a[7]
q_b[0] <= <GND>


|sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|sine64|cnt64:inst
q0 <= 74161:inst1.QA
clk => 74161:inst.CLK
clk => 74161:inst1.CLK
q1 <= 74161:inst1.QB
q2 <= 74161:inst1.QC
q3 <= 74161:inst1.QD
q4 <= 74161:inst.QA
q5 <= 74161:inst.QB


|sine64|cnt64:inst|74161:inst1
clk => f74161:sub.clk
ldn => f74161:sub.ldn
clrn => f74161:sub.clrn
enp => f74161:sub.enp
ent => f74161:sub.ent
d => f74161:sub.d
c => f74161:sub.c
b => f74161:sub.b
a => f74161:sub.a
qd <= f74161:sub.qd
qc <= f74161:sub.qc
qb <= f74161:sub.qb
qa <= f74161:sub.qa
rco <= f74161:sub.rco


|sine64|cnt64:inst|74161:inst1|f74161:sub
RCO <= 105.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 110.ACLR
CLRN => 99.ACLR
CLRN => 87.ACLR
CLRN => 9.ACLR
CLK => 110.CLK
CLK => 99.CLK
CLK => 87.CLK
CLK => 9.CLK
D => 113.IN0
LDN => 117.IN0
LDN => 77.IN1
LDN => 86.IN1
LDN => 98.IN1
LDN => 108.IN1
ENP => 106.IN0
ENP => 96.IN0
ENP => 89.IN0
ENP => 79.IN0
C => 101.IN0
B => 91.IN0
A => 76.IN0
ENT => 82.DATAIN
QD <= 110.DB_MAX_OUTPUT_PORT_TYPE
QC <= 99.DB_MAX_OUTPUT_PORT_TYPE
QB <= 87.DB_MAX_OUTPUT_PORT_TYPE
QA <= 9.DB_MAX_OUTPUT_PORT_TYPE


|sine64|cnt64:inst|74161:inst
clk => f74161:sub.clk
ldn => f74161:sub.ldn
clrn => f74161:sub.clrn
enp => f74161:sub.enp
ent => f74161:sub.ent
d => f74161:sub.d
c => f74161:sub.c
b => f74161:sub.b
a => f74161:sub.a
qd <= f74161:sub.qd
qc <= f74161:sub.qc
qb <= f74161:sub.qb
qa <= f74161:sub.qa
rco <= f74161:sub.rco


|sine64|cnt64:inst|74161:inst|f74161:sub
RCO <= 105.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 110.ACLR
CLRN => 99.ACLR
CLRN => 87.ACLR
CLRN => 9.ACLR
CLK => 110.CLK
CLK => 99.CLK
CLK => 87.CLK
CLK => 9.CLK
D => 113.IN0
LDN => 117.IN0
LDN => 77.IN1
LDN => 86.IN1
LDN => 98.IN1
LDN => 108.IN1
ENP => 106.IN0
ENP => 96.IN0
ENP => 89.IN0
ENP => 79.IN0
C => 101.IN0
B => 91.IN0
A => 76.IN0
ENT => 82.DATAIN
QD <= 110.DB_MAX_OUTPUT_PORT_TYPE
QC <= 99.DB_MAX_OUTPUT_PORT_TYPE
QB <= 87.DB_MAX_OUTPUT_PORT_TYPE
QA <= 9.DB_MAX_OUTPUT_PORT_TYPE