sine64.sim.rpt

chdl 64位计数器

; Total coverage as a percentage                      ;     100.00 % ;
; Total nodes checked                                 ; 39           ;
; Total output ports checked                          ; 38           ;
; Total output ports with complete 1/0-value coverage ; 38           ;
; Total output ports with no 1/0-value coverage       ; 0            ;
; Total output ports with no 1-value coverage         ; 0            ;
; Total output ports with no 0-value coverage         ; 0            ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                              ;
+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                 ; Output Port Name                                                                          ; Output Port Type ;
+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------------+
; |sine64|q[7]                                                                              ; |sine64|q[7]                                                                              ; pin_out          ;
; |sine64|q[6]                                                                              ; |sine64|q[6]                                                                              ; pin_out          ;
; |sine64|q[5]                                                                              ; |sine64|q[5]                                                                              ; pin_out          ;
; |sine64|q[4]                                                                              ; |sine64|q[4]                                                                              ; pin_out          ;
; |sine64|q[3]                                                                              ; |sine64|q[3]                                                                              ; pin_out          ;
; |sine64|q[2]                                                                              ; |sine64|q[2]                                                                              ; pin_out          ;
; |sine64|q[1]                                                                              ; |sine64|q[1]                                                                              ; pin_out          ;
; |sine64|q[0]                                                                              ; |sine64|q[0]                                                                              ; pin_out          ;
; |sine64|clk                                                                               ; |sine64|clk                                                                               ; out              ;
; |sine64|cnt64:inst|74161:inst|f74161:sub|97                                               ; |sine64|cnt64:inst|74161:inst|f74161:sub|97                                               ; out0             ;
; |sine64|cnt64:inst|74161:inst|f74161:sub|96                                               ; |sine64|cnt64:inst|74161:inst|f74161:sub|96                                               ; out0             ;
; |sine64|cnt64:inst|74161:inst|f74161:sub|84                                               ; |sine64|cnt64:inst|74161:inst|f74161:sub|84                                               ; out0             ;
; |sine64|cnt64:inst|74161:inst|f74161:sub|87                                               ; |sine64|cnt64:inst|74161:inst|f74161:sub|87                                               ; out              ;
; |sine64|cnt64:inst|74161:inst|f74161:sub|90                                               ; |sine64|cnt64:inst|74161:inst|f74161:sub|90                                               ; out0             ;
; |sine64|cnt64:inst|74161:inst|f74161:sub|89                                               ; |sine64|cnt64:inst|74161:inst|f74161:sub|89                                               ; out0             ;
; |sine64|cnt64:inst|74161:inst|f74161:sub|80                                               ; |sine64|cnt64:inst|74161:inst|f74161:sub|80                                               ; out0             ;
; |sine64|cnt64:inst|74161:inst|f74161:sub|9                                                ; |sine64|cnt64:inst|74161:inst|f74161:sub|9                                                ; out              ;
; |sine64|cnt64:inst|74161:inst|f74161:sub|78                                               ; |sine64|cnt64:inst|74161:inst|f74161:sub|78                                               ; out0             ;
; |sine64|cnt64:inst|74161:inst|f74161:sub|79                                               ; |sine64|cnt64:inst|74161:inst|f74161:sub|79                                               ; out0             ;
; |sine64|cnt64:inst|74161:inst1|f74161:sub|104                                             ; |sine64|cnt64:inst|74161:inst1|f74161:sub|104                                             ; out0             ;
; |sine64|cnt64:inst|74161:inst1|f74161:sub|110                                             ; |sine64|cnt64:inst|74161:inst1|f74161:sub|110                                             ; out              ;
; |sine64|cnt64:inst|74161:inst1|f74161:sub|107                                             ; |sine64|cnt64:inst|74161:inst1|f74161:sub|107                                             ; out0             ;
; |sine64|cnt64:inst|74161:inst1|f74161:sub|94                                              ; |sine64|cnt64:inst|74161:inst1|f74161:sub|94                                              ; out0             ;
; |sine64|cnt64:inst|74161:inst1|f74161:sub|99                                              ; |sine64|cnt64:inst|74161:inst1|f74161:sub|99                                              ; out              ;
; |sine64|cnt64:inst|74161:inst1|f74161:sub|97                                              ; |sine64|cnt64:inst|74161:inst1|f74161:sub|97                                              ; out0             ;
; |sine64|cnt64:inst|74161:inst1|f74161:sub|84                                              ; |sine64|cnt64:inst|74161:inst1|f74161:sub|84                                              ; out0             ;
; |sine64|cnt64:inst|74161:inst1|f74161:sub|87                                              ; |sine64|cnt64:inst|74161:inst1|f74161:sub|87                                              ; out              ;
; |sine64|cnt64:inst|74161:inst1|f74161:sub|90                                              ; |sine64|cnt64:inst|74161:inst1|f74161:sub|90                                              ; out0             ;
; |sine64|cnt64:inst|74161:inst1|f74161:sub|81                                              ; |sine64|cnt64:inst|74161:inst1|f74161:sub|81                                              ; out0             ;
; |sine64|cnt64:inst|74161:inst1|f74161:sub|9                                               ; |sine64|cnt64:inst|74161:inst1|f74161:sub|9                                               ; out              ;
; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[0] ; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[0] ; portadataout0    ;
; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[1] ; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[1] ; portadataout0    ;
; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[2] ; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[2] ; portadataout0    ;
; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[3] ; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[3] ; portadataout0    ;
; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[4] ; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[4] ; portadataout0    ;
; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] ; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] ; portadataout0    ;
; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[6] ; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[6] ; portadataout0    ;
; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] ; |sine64|rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] ; portadataout0    ;
+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------+
; Missing 1-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------+
; Missing 0-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Mar 24 15:19:49 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off sine64 -c sine64
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is     100.00 %
Info: Number of transitions in simulation is 3697
Info: Vector file sine64.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat Mar 24 15:19:49 2007
    Info: Elapsed time: 00:00:01