cnt64.vhd

chdl 64位计数器

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY cnt64 IS 
	port
	(
		clk :  IN  STD_LOGIC;
		q0 :  OUT  STD_LOGIC;
		q1 :  OUT  STD_LOGIC;
		q2 :  OUT  STD_LOGIC;
		q3 :  OUT  STD_LOGIC;
		q4 :  OUT  STD_LOGIC;
		q5 :  OUT  STD_LOGIC
	);
END cnt64;

ARCHITECTURE bdf_type OF cnt64 IS 

attribute black_box : boolean;
attribute noopt : boolean;

component \74161_0\
	PORT(CLRN : IN STD_LOGIC;
		 CLK : IN STD_LOGIC;
		 ENP : IN STD_LOGIC;
		 LDN : IN STD_LOGIC;
		 A : IN STD_LOGIC;
		 D : IN STD_LOGIC;
		 ENT : IN STD_LOGIC;
		 B : IN STD_LOGIC;
		 C : IN STD_LOGIC;
		 QC : OUT STD_LOGIC;
		 QB : OUT STD_LOGIC;
		 QA : OUT STD_LOGIC);
end component;
attribute black_box of \74161_0\: component is true;
attribute noopt of \74161_0\: component is true;

component \74161_1\
	PORT(CLRN : IN STD_LOGIC;
		 CLK : IN STD_LOGIC;
		 ENP : IN STD_LOGIC;
		 LDN : IN STD_LOGIC;
		 A : IN STD_LOGIC;
		 D : IN STD_LOGIC;
		 ENT : IN STD_LOGIC;
		 B : IN STD_LOGIC;
		 C : IN STD_LOGIC;
		 QD : OUT STD_LOGIC;
		 QC : OUT STD_LOGIC;
		 QB : OUT STD_LOGIC;
		 QA : OUT STD_LOGIC;
		 RCO : OUT STD_LOGIC);
end component;
attribute black_box of \74161_1\: component is true;
attribute noopt of \74161_1\: component is true;

signal	SYNTHESIZED_WIRE_17 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_18 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_19 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_20 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_21 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_16 :  STD_LOGIC;


BEGIN 
SYNTHESIZED_WIRE_19 <= '1';
SYNTHESIZED_WIRE_20 <= '1';
SYNTHESIZED_WIRE_21 <= '1';



b2v_inst : 74161_0
PORT MAP(CLRN => SYNTHESIZED_WIRE_17,
		 CLK => clk,
		 ENP => SYNTHESIZED_WIRE_18,
		 LDN => SYNTHESIZED_WIRE_19,
		 A => SYNTHESIZED_WIRE_19,
		 D => SYNTHESIZED_WIRE_19,
		 ENT => SYNTHESIZED_WIRE_18,
		 B => SYNTHESIZED_WIRE_19,
		 C => SYNTHESIZED_WIRE_19,
		 QC => SYNTHESIZED_WIRE_16,
		 QB => q5,
		 QA => q4);

b2v_inst1 : 74161_1
PORT MAP(CLRN => SYNTHESIZED_WIRE_17,
		 CLK => clk,
		 ENP => SYNTHESIZED_WIRE_20,
		 LDN => SYNTHESIZED_WIRE_21,
		 A => SYNTHESIZED_WIRE_21,
		 D => SYNTHESIZED_WIRE_21,
		 ENT => SYNTHESIZED_WIRE_20,
		 B => SYNTHESIZED_WIRE_21,
		 C => SYNTHESIZED_WIRE_21,
		 QD => q3,
		 QC => q2,
		 QB => q1,
		 QA => q0,
		 RCO => SYNTHESIZED_WIRE_18);

SYNTHESIZED_WIRE_17 <= NOT(SYNTHESIZED_WIRE_16);


END;