cnt64.map.qmsg

chdl 64位计数器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 24 09:04:51 2008 " "Info: Processing started: Mon Mar 24 09:04:51 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cnt64 -c cnt64 --convert_bdf_to_vhdl=F:/zyp/sine/cnt64/cnt64.bdf " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cnt64 -c cnt64 --convert_bdf_to_vhdl=F:/zyp/sine/cnt64/cnt64.bdf" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt64.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file cnt64.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 cnt64 " "Info: Found entity 1: cnt64" {  } { { "F:/zyp/sine/cnt64/cnt64.bdf" "" { Schematic "F:/zyp/sine/cnt64/cnt64.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cnt64 " "Info: Elaborating entity \"cnt64\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_IS_MEGAFUNCTION" "74161 " "Warning: Found Altera-specific megafunction, primitive or component \"74161\"" {  } { { "F:/zyp/sine/cnt64/cnt64.bdf" "" { Schematic "F:/zyp/sine/cnt64/cnt64.bdf" { { 200 320 440 384 "inst" "" } } } }  } 0 0 "Found Altera-specific megafunction, primitive or component \"%1!s!\"" 0 0}
{ "Warning" "WGDFX_IS_MEGAFUNCTION" "74161 " "Warning: Found Altera-specific megafunction, primitive or component \"74161\"" {  } { { "F:/zyp/sine/cnt64/cnt64.bdf" "" { Schematic "F:/zyp/sine/cnt64/cnt64.bdf" { { 200 552 672 384 "inst1" "" } } } }  } 0 0 "Found Altera-specific megafunction, primitive or component \"%1!s!\"" 0 0}
{ "Warning" "WGDFX_DESIGN_NAME_CONTAIN_NUMBER" "74161_0 " "Warning: Design name for \"74161_0\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" {  } { { "F:/zyp/sine/cnt64/cnt64.bdf" "" { Schematic "F:/zyp/sine/cnt64/cnt64.bdf" { } } }  } 0 0 "Design name for \"%1!s!\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" 0 0}
{ "Warning" "WGDFX_DESIGN_NAME_CONTAIN_NUMBER" "74161_1 " "Warning: Design name for \"74161_1\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" {  } { { "F:/zyp/sine/cnt64/cnt64.bdf" "" { Schematic "F:/zyp/sine/cnt64/cnt64.bdf" { } } }  } 0 0 "Design name for \"%1!s!\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 24 09:04:51 2008 " "Info: Processing ended: Mon Mar 24 09:04:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}