micro.v

i2c的verilog代码

//----------------------------------------------------------------------------
// 
//  Name:  micro.v   
// 
//  Description: Microprocessor simulation model for I2C serial controller
// 
//  $Revision: 1.0 $          
//  
//  Copyright 2004 Lattice Semiconductor Corporation.  All rights reserved.
//
//----------------------------------------------------------------------------
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//----------------------------------------------------------------------------
//
//    Lattice Semiconductor Corporation
//    5555 NE Moore Court
//    Hillsboro, OR 97124
//    U.S.A
//
//    TEL: 1-800-Lattice (USA and Canada)
//    408-826-6000 (other locations)
//
//    web: http://www.latticesemi.com/
//    email: [e-mail]
// 
//----------------------------------------------------------------------------

`timescale 1 ns /  100 ps

/*
Module  micro
This is the microprocessor simulator for the I2C Controller. 
*/


module micro(   clk,
                rst_l,
                data,              
                addr,
                cs_l,
                ack_l,
                rd_wr_l);

//-------------------------------------------------------------------
// port list

input           clk;
input           rst_l;
input           ack_l;

inout   [7:0]   data;

output  [1:0]   addr;
output          cs_l;
output          rd_wr_l;                

//-------------------------------------------------------------------
// registers & wires

reg     [1:0]   addr;
reg             cs_l;
reg             rd_wr_l;
reg     [7:0]   data_out;

reg             i2c_rdy;

reg     [7:0]   cntr;

wire    [7:0]   data;
reg     [7:0]   data_ret;

//--------------------------------------
// variables

integer num_errors;


//-------------------------------------------------------------------
// tri-state buffer

assign data = (!rd_wr_l) ? data_out : 8'bz;

//-------------------------------------------------------------------
// initial block

initial begin
    i2c_rdy  <= 1'b0;
    cntr     <= 8'b0;
    addr     <= 2'b0;
    cs_l     <= 1'b1;
    rd_wr_l  <= 1'b1;
    data_out <= 8'b0;
    
   // set number of errors to 0
    num_errors = 0;
    
    wait (rst_l)
    $display($time,": Coming out of Reset");
    $display();
    
 
   // writing word address 8'h55
   write(8'h55);
 
 
   // monitor i2c_rdy
 
   monitor_i2c_rdy;
 
   // read data expect 8'h55 cause that's what's stored in 55
   read_data(8'h55); 
        
   // kill time
   kill_time;
 

   // writing word address 8'haa
   write(8'haa);

   
   // monitor i2c_rdy
 
   monitor_i2c_rdy; 

   // read data expect 8'haa cause that's what's stored in aa
   read_data(8'haa);
 
   $display($time, " << Simulation complete with %d errors >>", num_errors);
   $stop;
 end
 
 
 
 //------------------------------------------------------
 // Declare tasks
 
 task write;
   input [7:0] address;
 
   begin
   $display($time,": Writing Word Address");
    addr     <= 2'b00;
    rd_wr_l  <= 1'b0;
    data_out <= address;
    @(posedge clk);
    cs_l     <= #1 1'b0;
    wait (!ack_l);
    @(posedge clk)
    cs_l     <= #1 1'b1;
    @(posedge clk);
    rd_wr_l  <= #1 1'b1;
   end
   
 endtask //of write
 
 
 task monitor_i2c_rdy;
   begin
    // clearing i2c_rdy flag
    i2c_rdy  <= 1'b0;
    cntr = 0;
    #1;
    
    while(!i2c_rdy && (cntr != 255)) begin
        #10000;
        addr     <= 2'b10;
        @(posedge clk);
        cs_l     <= #1 1'b0;
        wait (!ack_l);
        cntr    <= cntr + 1;
        i2c_rdy <= data[7];
        @(posedge clk)
        cs_l     <= #1 1'b1;
        end
 
    if (i2c_rdy == 0) begin 
      $display($time, " %m << ERROR: i2c never responded with data>>");
      num_errors = num_errors + 1;
    end
 
    $display($time, " leaving monitor ");
 
   i2c_rdy <= 1'b0;
   
   end
  endtask //of monitor_i2c_rdy
  
 
   task read_data;
      input [7:0] expected;
 
   begin      
     #1000;    
    $display($time,": Reading Data");
    addr     <= 2'b01;
    @(posedge clk);
    cs_l     <= #1 1'b0;
    wait (!ack_l);
    $display($time,": Data = %h",data);
    data_ret = data;
    @(posedge clk)
    cs_l     <= #1 1'b1;
    rd_wr_l  <= #1 1'b1; 
 
    if (data_ret !== expected) begin 
      $display($time, " %m << ERROR: data returned = %b data_expected = %b ", data_ret, expected);
     num_errors = num_errors + 1; 
    end
   end   
    endtask //of read_data
 
 
    task kill_time;
      begin
      #10000; // wait some time
      end
    endtask //of kill_time
    
    
endmodule

//------------------------------- E O F --------------------------------------