majority_voter.map.summary

来自「Verylog编写的 Quartus II平台的简单设计实例 附仿真波形」· SUMMARY 代码 · 共 8 行

Analysis & Synthesis Status : Successful - Mon May 19 20:35:24 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : MAJORITY_VOTER
Top-level Entity Name : MAJORITY_VOTER
Family : MAX7000S
Total macrocells : 2
Total pins : 5