majority_voter.qsf

Verylog编写的 Quartus II平台的简单设计实例 附仿真波形

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		MAJORITY_VOTER_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7128SLC84-15"
set_global_assignment -name TOP_LEVEL_ENTITY MAJORITY_VOTER
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:50:16  MAY 19, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name VERILOG_FILE MAJORITY_VOTER.v
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_location_assignment PIN_41 -to L3
set_location_assignment PIN_40 -to L4
set_location_assignment PIN_65 -to SW1
set_location_assignment PIN_55 -to SW2
set_location_assignment PIN_52 -to SW3
set_global_assignment -name VECTOR_WAVEFORM_FILE MAJORITY_VOTER.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE MAJORITY_VOTER.sim.vwf