traffic.v

利用Verilog实现交通灯控制 Quartus II平台实现仿真

//交通灯控制电路
module traffic(L,CLK);
output [6:1] L;
input CLK;
reg [1:0] LSTATUS;
reg [4:0] LTIME;
reg [6:1] LREG;
reg CLOCK;
always @ (posedge CLK)
CLOCK=~CLOCK;
always @ (posedge CLOCK)
  begin
  if (LSTATUS==2'd0)
    begin
    if (LTIME==5'd0)
      begin
      LSTATUS=2'd1;
      LTIME=5'd3;
      LREG=6'b001010;
      end
    else
      begin
      LTIME=LTIME-1;
      end
    end
  else if (LSTATUS==2'd1)
      begin
      if (LTIME==5'd0)
        begin
        LSTATUS=2'd2;
        LTIME=5'd29;
        LREG=6'b100001;
        end
      else
        begin
        LTIME=LTIME-1;
        end
      end
  else if (LSTATUS==2'd2)
    begin
    if (LTIME==5'd0)
      begin
      LSTATUS=2'd3;
      LTIME=5'd3;
      LREG=6'b010001;
      end
    else
      begin
      LTIME=LTIME-1;
      end
    end
  else if (LSTATUS==2'd3)
    begin
    if (LTIME==5'd0)
      begin
      LSTATUS=2'd0;
      LTIME=5'd19;
      LREG=6'b001100;
      end
    else
      begin
      LTIME=LTIME-1;
      end
    end
  end
assign L=LREG;
endmodule