traffic.tan.rpt

利用Verilog实现交通灯控制 Quartus II平台实现仿真

; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; traffic|LSTATUS.state_bit_0 ; LREG[4]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LTIME[4]                    ; LREG[4]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LTIME[3]                    ; LREG[4]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LTIME[2]                    ; LREG[4]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LTIME[1]                    ; LREG[4]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LREG[4]                     ; LREG[4]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LTIME[0]                    ; LREG[1]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; traffic|LSTATUS.state_bit_1 ; LREG[1]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; traffic|LSTATUS.state_bit_0 ; LREG[1]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LTIME[4]                    ; LREG[1]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LTIME[3]                    ; LREG[1]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LTIME[2]                    ; LREG[1]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LTIME[1]                    ; LREG[1]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LREG[1]                     ; LREG[1]                     ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
+-------+----------------------------------+-----------------------------+-----------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+---------+------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To   ; From Clock ;
+-------+--------------+------------+---------+------+------------+
; N/A   ; None         ; 17.000 ns  ; LREG[4] ; L[4] ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; LREG[1] ; L[1] ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; LREG[5] ; L[5] ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; LREG[6] ; L[6] ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; LREG[3] ; L[3] ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; LREG[2] ; L[2] ; CLK        ;
+-------+--------------+------------+---------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue May 20 20:29:47 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off traffic -c traffic
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "CLOCK" as buffer
Info: Clock "CLK" has Internal fmax of 76.92 MHz between source register "CLOCK" and destination register "CLOCK" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC66; Fanout = 14; REG Node = 'CLOCK'
        Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC66; Fanout = 14; REG Node = 'CLOCK'
        Info: Total cell delay = 8.000 ns ( 100.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC66; Fanout = 14; REG Node = 'CLOCK'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC66; Fanout = 14; REG Node = 'CLOCK'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock "CLK" to destination pin "L[4]" through register "LREG[4]" is 17.000 ns
    Info: + Longest clock path from clock "CLK" to source register is 12.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC66; Fanout = 14; REG Node = 'CLOCK'
        Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC51; Fanout = 6; REG Node = 'LREG[4]'
        Info: Total cell delay = 10.000 ns ( 83.33 % )
        Info: Total interconnect delay = 2.000 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC51; Fanout = 6; REG Node = 'LREG[4]'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'L[4]'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Tue May 20 20:29:48 2008
    Info: Elapsed time: 00:00:04