fenpin.vhd

简单的数字频率计

library IEEE;
use IEEE.std_logic_1164.all;

entity fenpin is
port(source:in std_logic;
	 d:out std_logic);
end fenpin;

architecture fenpin_arch of fenpin is
signal tp:std_logic;
begin
  process(source)
	begin
	if (source'event)and(source='1') then 
	  if tp='0' then tp<='1'; else tp<='0';end if;
	end if;
	d<=tp;
  end process;
end fenpin_arch;