xx2.vhd

来自「简单的数字频率计」· VHDL 代码 · 共 21 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity xx2 is
port(d:unsigned(1 downto 0);
		x1,x2,x3,x4:out std_logic);
end xx2;

architecture xx2_arch of xx2 is
signal tp:unsigned(1 downto 0);
begin
  process(d)begin
    tp<=d;
	case tp is
     when "00" =>x1<='1';x2<='1';x3<='1';x4<='0';
	 when others =>x1<='0';x2<='0';x3<='0';x4<='1';
    end case;
  end process;
end xx2_arch;