sel.vhd

来自「简单的数字频率计」· VHDL 代码 · 共 18 行

library IEEE;
use IEEE.std_logic_1164.all;

entity sel is
port(test,selec,meas:in std_logic;
	 cp:out std_logic);
end sel;

architecture sel_arch of sel is
begin
  process
	begin
	if selec='0' then cp<=test;
	else cp<=meas;
    end if;
  end process;
end sel_arch;