tsc.vhd

来自「简单的数字频率计」· VHDL 代码 · 共 21 行

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity tsc is
port(a:in unsigned(3 downto 0);
     b:out unsigned(1 downto 0));
end tsc;

architecture tsc_arch of tsc is
begin
  process
  variable tp:unsigned;
	begin
	tp:=a;
	tp:=tp/4;
    b<=tp;
	end process;
end tsc_arch;