jishu1.vhd

来自「简单的数字频率计」· VHDL 代码 · 共 29 行

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity jishu1 is
  port (cp:in std_logic;
		rd:in std_logic;
		c:out std_logic;
		q:out unsigned(3 downto 0));
end jishu1;

architecture jishu1_arch of jishu1 is
signal iq:unsigned(3 downto 0);
signal tc:std_logic;
begin
process(cp,rd,iq)
begin 
  if rd='0' then iq<="0000";tc<='0';
  elsif (cp'event)and(cp='1') then iq<=iq+1;
  if iq=15 then tc<='1'; end if;
  end if;
end process;
process(rd)
begin
if (rd='0')and(rd'event) then q<=iq;c<=tc;
end if;
end process;
end jishu1_arch;