sc1.vhd

来自「简单的数字频率计」· VHDL 代码 · 共 22 行

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity sc1 is
port(cin:in std_logic;
     a,b,c,d:in unsigned(3 downto 0);
	 dx,dz,dy:out unsigned(3 downto 0);
	 dw,alert:out std_logic);
end sc1;

architecture sc1_arch of sc1 is
begin
  process
	begin
    if cin='1' then alert<='1';
	elsif a>0 then dw<='1';dx<=a;dy<=b;dz<=c;alert<='0';
	else dw<='0';dx<=b;dy<=c;dz<=d;alert<='0';
	end if;
  end process;
end sc1_arch;